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| ICs for Communications Analog Line Interface Solution - ALIS ALIS V3 PSB 4595 Version 2.1 PSB 4596 Version 3.1 Preliminary Data Sheet 04.99 DS 1 * PSB 4595 / PSB 4596 Revision History: Previous Version: Page Page (in previous (in current Version) Version) Subjects (major changes since last revision) Current Version: 04.99 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com * ABM(R), AOP(R), ARCOFI(R), ARCOFI(R)-BA, ARCOFI(R)-SP, DigiTape(R), EPIC(R)-1, EPIC(R)-S, ELIC(R), FALC(R)54, FALC(R)56, FALC(R)-E1, FALC(R)-LH, IDEC(R), IOM(R), IOM(R)-1, IOM(R)-2, IPAT(R)-2, ISAC(R)-P, ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P TE, ITAC(R), IWE(R), MUSAC(R)-A, OCTAT(R)-P, QUAT(R)-S, SICAT(R), SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R) are registered trademarks of Infineon Technologies AG. ACETM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUTTM are trademarks of Infineon Technologies AG. Edition 04.99 Published by Infineon Technologies AG i. Gr., SC, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG i.Gr. 1999. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Table of Contents 1 1.1 1.2 1.3 1.3.1 1.3.2 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.3.10 3.3.11 3.3.12 3.3.13 3.4 3.4.1 3.4.2 4 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.3 Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 ALIS with DSP-based Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 ALIS with Software Modem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Pin Definitions of ALIS-A (PSB 4595) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Pin Definitions of ALIS-D (PSB 4596) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Control: ALIS-A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 VDDA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Hybrid Circuit and Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Analog/Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Digital Isolation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Caller-ID Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Hardware Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Digital Filter Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Control: ALIS-D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 BUZZER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Multiplex and Non-Multiplex Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Master and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Ringing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Caller-ID State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Conversation State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Pulse Dialing State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Sleep State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Operational Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Preliminary Data Sheet 3 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Table of Contents 5 5.1 5.1.1 5.1.1.1 5.1.1.2 5.1.1.3 5.1.1.4 5.1.1.5 5.1.1.6 5.1.1.7 5.1.2 5.1.2.1 5.1.2.2 5.1.3 5.1.3.1 5.1.3.2 5.1.3.3 5.1.3.4 5.1.4 5.1.5 5.2 5.3 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.1.1 7.5.1.2 7.5.2 7.5.2.1 7.5.2.2 7.6 7.6.1 7.6.2 7.6.3 Page Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Host Interface: Control and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Master/Slave Modes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Multiplex Mode with Cascaded Devices . . . . . . . . . . . . . . . . . . . . . . .39 Non-multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Multiple ALIS Chipsets in Non-multiplex Mode . . . . . . . . . . . . . . . . . .43 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Telephone Line Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Pulse Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Metering Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Caller-ID Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Digital Isolation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Setup during Reset of the ALIS-D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Configuration of the ALIS-D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Determination of the State of the ALIS-D . . . . . . . . . . . . . . . . . . . . . . . . . .81 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Single-Step Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Single-Step Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Single-Step Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Two-Step Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Two-Step Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Two-Step Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Static Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Dynamic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Interrupt Handling for the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 4 04.99 Preliminary Data Sheet PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Table of Contents 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 10 11 12 Page Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Extreme Absolute Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 ALIS-A DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 ALIS-D DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Absolute Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Gain Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Preliminary Data Sheet 5 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS List of Figures Figure 1-1 Figure 1-2 Figure 1-3 Figure 2-1 Figure 2-2 Figure 3-1 Figure 3-2 Figure 3-3 Figure 4-1 Figure 4-2 Figure 4-3 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Figure 5-10 Figure 5-11 Figure 5-12 Figure 5-13 Figure 5-14 Figure 5-15 Figure 5-16 Figure 5-17 Figure 5-18 Figure 5-19 Figure 5-20 Figure 5-21 Figure 7-1 Figure 8-1 Figure 8-2 Figure 8-3 Page Logic Symbol of the ALIS Chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DSP-based Modem Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Software Modem Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Pin Configuration of the ALIS-A (PSB 4595) (Top View) . . . . . . . . . . . .15 Pin Configuration of the ALIS-D (PSB 4596) (Top View) . . . . . . . . . . . .15 ALIS Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Clocking of the ALIS in Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . .25 Clocking of the ALIS in Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Group Delay Distortion, Transmit and Receive (High-Pass Filter On) . .31 Out-of-Band Receive (High-Pass Filter On). . . . . . . . . . . . . . . . . . . . . .31 Out-of-Band Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 SDI in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 SDI Framing in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 SDI in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 SDI Framing in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 ALIS-D in Multiplex Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Multiplex Mode (SWAP ='0'): Write Access . . . . . . . . . . . . . . . . . . . . . .38 Multiplex Mode (SWAP ='0'): Read Access . . . . . . . . . . . . . . . . . . . . . .38 Multiplex Mode (SWAP = '1'): Write Access . . . . . . . . . . . . . . . . . . . . .39 ALIS-D in Multiplex/Master Mode with an Additional Codec . . . . . . . . .40 Framing for an Additional Codec: Read Access . . . . . . . . . . . . . . . . . .40 Dual-Line Modem: Two ALIS Chipsets . . . . . . . . . . . . . . . . . . . . . . . . .41 Framing for Two ALIS-D Chips: Read Access . . . . . . . . . . . . . . . . . . . .41 ALIS-D in Non-multiplex/Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . .42 Framing for Read Access to SCI in Non-multiplex Mode. . . . . . . . . . . .42 Framing for Write Access to SCI in Non-multiplex Mode . . . . . . . . . . . .43 Connection of ALIS-A to Telephone Line. . . . . . . . . . . . . . . . . . . . . . . .44 Fitting Voltage/Current Relationship into Example Mask . . . . . . . . . . . .46 Caller-ID Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Caller ID by Line Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Isolation by Capacitive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Isolation by Inductive Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Scanning of an Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Preliminary Data Sheet 6 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS List of Tables Table 2-1 Table 2-2 Table 4-1 Table 5-1 Table 5-3 Table 5-2 Table 5-4 Table 5-5 Table 5-6 Table 6-1 Table 6-2 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 8-1 Table 8-2 Table 9-1 Table 9-2 Table 9-3 Table 9-4 Table 9-5 Table 9-6 Table 9-7 Page ALIS-A Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ALIS-D Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DAA Performance Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Mapping of SCI Signals to ALIS-D Pin Symbols . . . . . . . . . . . . . . . . . 33 Master/Slave Modes of ALIS-D: SDI Roles . . . . . . . . . . . . . . . . . . . . . 34 Mapping of SDI Signals to ALIS-D Pin Symbols . . . . . . . . . . . . . . . . . 34 Multiplex Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 External Components PSB 4595 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Storing the Caller ID Signal in CID-RAM . . . . . . . . . . . . . . . . . . . . . . . 48 ALIS-D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Programming Examples for K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Setup Sequence of the ALIS-D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Configuration Sequence of the ALIS-D . . . . . . . . . . . . . . . . . . . . . . . . 80 Configuration Sequence of the ALIS-D . . . . . . . . . . . . . . . . . . . . . . . . 81 Interrupt Register R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Static Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Dynamic Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Serial Control Interface Timing Characteristics . . . . . . . . . . . . . . . . . . 91 Serial Data Interface Timing Characteristics . . . . . . . . . . . . . . . . . . . . 93 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 94 Extreme Absolute Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 DC Characteristics of the ALIS-A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 DC Characteristics of the ALIS-D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Absolute Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Gain Tracking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Preliminary Data Sheet 7 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Preface This document, the Preliminary Data Sheet, describes the functionality, application and software issues of the Infineon Technologies Analog Line Interface Solution (ALIS) chipset, ALIS-A and ALIS-D. It is intended to provide as well a hardware as a software design engineer with the most important information needed to evaluate and use the ALIS chipset for an application. Organization of this Document This Preliminary Data Sheet is organized as follows: * Chapter 1, Overview Includes the general description, features list, logic symbol, and summary of typical applications. * Chapter 2, Pin Descriptions Includes the configuration of pins, descriptions of their functions, and the interconnection of the ALIS-A with the ALIS-D. * Chapter 3, Functional Description Summarizes the functional architecture and operating modes of the ALIS. * Chapter 4, Operational Description Summarizes the different operating states, and the performance of the ALIS as a Data Access Arrangement (DAA). * Chapter 5, Interface Descriptions Summarizes the hardware and software aspects of the Serial Control Interface (SCI), Serial Data Interface (SDI), telephone line connection, and Caller-ID interface. * Chapter 6, Register Description Contains a map of registers and their descriptions. * Chapter 7, Programming Describes how to address the registers of the ALIS-D for programming. * Chapter 8, Timing Diagrams Contains the timing parameters for all signals. * Chapter 9, Electrical Characteristics States the recommended operating conditions, absolute extreme range, DC and AC characteristics. * Chapter 10, Package Outlines Includes package outlines for both ALIS-A and ALIS-D components. * Chapter 11, Appendix Includes a glossary. * Chapter 12, Index Related Documentation Additional documentation for the ALIS chipset includes a "Product Brief", "Product Overview" and assorted "Application Notes". Preliminary Data Sheet 8 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Overview 1 Overview The Analog Line Interface Solution (ALIS) chipset is a complete analog modem front-end that integrates a fully programmable Data Access Arrangement (DAA) with a high quality codec. It can be used for analog subscriber equipment, such as modems, fax, or voice appliances. It provides: * Modem performance improved by digital isolation interface: greater linearity, reduced noise; * Adaptation to different countries' line requirements by downloading of coefficients; * Form-factor and power consumption optimized for portable and battery-operated equipment; * Conformance with PC 98/PC 99 on Caller-ID storage, wake-up on incoming calls, and power-saving modes; and * Demonstrated worldwide compliance to telecom and safety standards with prehomologated reference systems. The ALIS chipset consists of an analog component--the ALIS-A (PSB 4595)--and a digital part--the ALIS-D (PSB 4596). The ALIS-A, which is powered by the loop current of the telephone line, implements the line interface, ring detector, hybrid, filters and the codec. The ALIS-D incorporates programmable digital filter structures that allow very flexible line adaptation. It provides dialing functions, captures Caller-ID information and stores it in a register, even when the device is in power-down state. The ALIS chipset uses small 24- and 28-pin packages and conforms to PC-Card standards. Preliminary Data Sheet 9 04.99 Analog Line Interface Solution - ALIS ALIS V3 PSB 4595 PSB 4596 ALIS-A Version 2.1 ALIS-D Version 3.1 1.1 Features Cost savings features * Integrates two-wire Tip/Ring interface, hybrid, codec, and digital filter structures for flexible line adaptation. * Integrates ring detector, DTMF and pulse dialing. * Digital isolation interface between ALIS-A and ALISD chips eliminates voice band transformer. * Reduces Bill of Materials (BOM). * Phase-Locked Loop allows sampling rates from 7.2 to 32 kHz. * Eliminates requirement for country-specific designs and optimization. * Reference approvals reduce expenses and time for homologations. P-TSSOP-24 P-TSSOP-28 World-wide compliance features * Provides a Data Access Arrangement (DAA) configurable for international application. * Fully programmable subscriber line characteristics: Transhybrid loss, AC impedance, DC characteristics, receive and transmit levels. * Telco reference approvals according to FCC Part 68 (USA), CTR-21 (UK, future European Standard), B-11 23A (France), BAPT 223 ZV5 (Germany), JATE (Japan), TS002 (Australia). * Safety reference approval according to IEC 950, EN 60 950, covering: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Portugal, Spain, Switzerland, United Kingdom. Type PSB 4595 PSB 4596 Preliminary Data Sheet Package P-TSSOP-24 P-TSSOP-28 10 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Overview * Programmable Caller-ID receiver conforms to Bell 202, CCITT V.23, and Bellcore specifications TR-NWT-000030 and SR-TSV-002476. Performance features * * * * 16-bit linear codec meets V.34 and V.90 modem requirements. Programmable symbol and data rates. Reduced noise due to a short analog signal path. Excellent transmission quality (even in low-frequency range) provides superior modem performance, particularly for V.90 modems. * Provides Caller-ID storage. Time-to-market * * * * Requires only one hardware design for the global market. Predefined country-specific coefficient sets available. Evaluation system available. Excellent development tool support. Form factor * Small, PC-Card compliant packages (P-TSSOP24, P-TSSOP28). * Ideal for PC-Card applications (no bulky voice band transformer). * Minimizes the number of discrete components. Power saving features * ALIS-A is powered by the Tip/Ring loop current. * ALIS-D supports two power management states to reduce power consumption. * Supports PC power management functions with wake-up signal and Caller-ID storage (PC 98 ready). Preliminary Data Sheet 11 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Overview 1.2 * Logic Symbol RESET MCLK1/2 BM VDD GND Serial Data Interface (SDI) GPO ALIS-D PSB 4596 Serial Control Interface (SCI) (optional) Caller-ID Interface GPIO SLEEP Digital Isolation Interface ALIS-A PSB 4595 GPI Tip/Ring Figure 1-1 Logic Symbol of the ALIS Chipset Note: The Serial Control Interface SCI can optionally be used for programming the chipset (see Chapter 5.1.1.1). Preliminary Data Sheet 12 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Overview 1.3 Typical Applications The ALIS can be used in different modem applications to connect the data pump to the Tip/Ring wire. 1.3.1 * ALIS with DSP-based Modem For a modem data pump, the ALIS provides the front-end to the Tip/Ring. * 'DWD 3XPS 9 9 SDI $/,6' 36% Digital Isolation Interface $/,6$ 36% 7LS5LQJ SCI SDI: Serial Data Interface SCI: Serial Control Interface Figure 1-2 DSP-based Modem Application Isolation is provided by a digital Isolation interface between the ALIS-A and the ALIS-D (see Chapter 5.1.5). This allows very flat frequency response over the entire voice band, even at low frequencies. Preliminary Data Sheet 13 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Overview 1.3.2 ALIS with Software Modem The ALIS can also be used in software modems, in which V.34 or the V.90 modem algorithms are run on the host. In this application, the Serial Data Interface (SDI) is connected to the USB or PCI interface via a FIFO structure. * *. $/,6' 36% SDI SCI Digital Isolation Interface $/,6$ 36% 7LS5LQJ PCI/USB Bridge PCI or USB Figure 1-3 Software Modem Application Preliminary Data Sheet 14 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Pin Descriptions 2 2.1 * Pin Descriptions Pin Configurations P-TSSOP24 CAP1 CAP2 VREF TIP TIP_AC RING RING_AC GPO_0_A GPO_1Q_A B22 B21 A22 1 2 3 4 ALIS-A 5 6 PSB 4595 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 GNDA T1G VDDA VDDA_SENS NC T2G GPI_0_A GPI_1_A TEST C21 C22 A21 Figure 2-1 * Pin Configuration of the ALIS-A (PSB 4595) (Top View) P-TSSOP28 A12 B11 B12 CID_T CID_R SLEEP BM GPIO_D BUZZER SCI_CS/SWAP SCI_CLK/MODE SCI_OUT SCI_IN INT 1 2 3 4 ALIS-D 5 6 PSB 4596 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A11 C12 C11 VDD GND RESET GPO_D MCLK2 MCLK1 FSC2 SDI_CLK SDI_TX SDI_RX FSC Figure 2-2 Pin Configuration of the ALIS-D (PSB 4596) (Top View) Preliminary Data Sheet 15 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Pin Descriptions 2.2 Table 2-1 Pin Definitions of ALIS-A (PSB 4595) ALIS-A Pin Definitions Pin 22 24 4 5 6 7 23 19 Type Power Power I I I I O O I I/O I/O Description VDDA Analog supply voltage. Analog ground All signals are referenced to this pin. Tip Tip AC+DC input. Tip AC Tip AC input. Ring Ring AC+DC input. Ring Ring AC input. Transistor 1 Gate Gate for external transistor T1 (AC/DC control). Transistor 2 Gate Gate for external transistor T2 (VDDA control). Supply Voltage Sense VDDA sense input. Reference Voltage Must connect to GNDA via an external capacitor. Capacitance 1 Must connect to pin CAP2 via an external capacitor for DC filtering. Capacitance 2 Must connect to pin CAP1 via an external capacitor for DC filtering. General Purpose Input 0 Auxiliary input pin 0. Tied to GNDA or VDDA if not in use. General Purpose Input 1 Auxiliary input pin 1. Tied to GNDA or VDDA if not in use. General Purpose Output 0 Auxiliary output pin 0. Disconnected if not in use. 16 04.99 Symbol VDDA GNDA TIP TIP_AC RING RING_AC T1G T2G VDDA_SENS 21 VREF CAP1 3 1 CAP2 2 I/O GPI_0_A 18 I GPI_1_A 17 I GPO_0_A 8 O Preliminary Data Sheet PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Pin Descriptions Table 2-1 Symbol GPO_1Q_A TEST A21 ALIS-A Pin Definitions (cont'd) Pin 9 16 13 Type O I I Description General Purpose Output 1 Auxiliary output pin 1. Disconnected if not in use. Test Must connect to GNDA. Digital Isolation Interface to ALIS-D: Must be connected to pin A11 of ALIS-D (see Chapter 3.3.5) Digital Isolation Interface to ALIS-D: Must be connected to pin A12 of ALIS-D (see Chapter 3.3.5) Digital Isolation Interface to ALIS-D: Must be connected to pin B11 of ALIS-D (see Chapter 3.3.5) Digital Isolation Interface to ALIS-D: Must be connected to pin B12 of ALIS-D (see Chapter 3.3.5) Digital Isolation Interface to ALIS-D: Must be connected to pin C11 of ALIS-D (see Chapter 3.3.5) Digital Isolation Interface to ALIS-D: Must be connected to pin C12 of ALIS-D (see Chapter 3.3.5) Not Connected Reserved. A22 12 I B21 11 O B22 10 O C21 15 I C22 14 I NC 20 n/a Preliminary Data Sheet 17 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Pin Descriptions 2.3 Table 2-2 Symbol VDD Pin Definitions of ALIS-D (PSB 4596) ALIS-D Pin Definitions Pin 25 Type Power Description VDD Digital supply voltage. Power supply for the digital circuitry: + 3.3 VDC. Digital Ground All signals are referenced to this pin. Master Clock 1 Either connected to one pin of an external crystal or driven by an external clock. Master Clock 2 When MCLK1 is connected to an external clock, MCLK2 is left open; when MCLK1 is connected to an external crystal, MCLK2 is connected to the second pin. Reset Input Resets the device; active low signal. Frame Synchronization Clock As input: indicates beginning of the frame. FSC must be synchronous with SDI_CLK (Slave Mode). As output: indicates beginning of a new frame (Master Mode). SDI Transmit (from Host) Serial Data Interface (SDI): Transmit data input from Host. Non-multiplex Mode: 16-bit modem data only. Multiplex Mode: 16-bit modem data plus 16-bit control data for every FSC frame. SDI Receive (to Host) Serial Data Interface (SDI): Receive data output to Host; tristate if not active (switchable pull-up). Non-multiplex Mode: 16-bit modem data only. Multiplex Mode: 16-bit modem data plus 16-bit control data for every FSC frame. SDI Clock Serial Data Interface (SDI): Clock for serial data transfer. GND MCLK1 24 20 Power I MCLK2 21 O RESET FSC 23 15 I I/O SDI_TX 17 I SDI_RX 16 O SDI_CLK 18 I/O Preliminary Data Sheet 18 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Pin Descriptions Table 2-2 Symbol FSC2 ALIS-D Pin Definitions (cont'd) Pin 19 Type O Description Frame Synchronization Clock 2 Second FSC to synchronize slave devices. The signal has duration of one SDI_CLK period. Interrupt Interrupt output pin; open drain, active low signal. Internal 33 k pull-up resistor. Bus Master Determines Master or Slave Mode of the Serial Data Interface. To set Master Mode: at rising edge of RESET signal, set to high and hold. To set Slave Mode: at rising edge of RESET signal, set to low and hold. Sleep Indicates that ALIS-D is in the Sleep state. SCI Clock Serial Control Interface: Clock for control communications in Non-multiplex Mode. Also Mode set. To set Multiplex (Non-multiplex) Mode: at rising edge of RESET signal, set to high (low) and hold for at least 10 MCLK cycles. Chip Select/Swap Non-multiplex Mode: SCI: Chip select, active low signal. Multiplex Mode: set during Reset and at rising edge of FSC, determines order of SDI and SCI bits for next FSC frame. Low: first 16 bits for SDI, next 16 bits for SCI; high: reversed. SCI Incoming Non-multiplex Mode: Serial Control Interface (SCI): control information from Host. Multiplex Mode: not used. Tie to high or low if not in use. SCI Outgoing Non-multiplex Mode: Serial Control Interface (SCI): control information to Host. Multiplex Mode: not used, leave open. 19 04.99 INT 14 O BM 7 I SLEEP SCI_CLK/ MODE 6 11 O I SCI_CS/ SWAP 10 I SCI_IN 13 I SCI_OUT 12 O Preliminary Data Sheet PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Pin Descriptions Table 2-2 Symbol CID_T ALIS-D Pin Definitions (cont'd) Pin 4 Type I Description CID Tip input Tip input for Caller-ID comparator: must be connected to tip through a capacitor. CID Ring input Ring input for Caller-ID comparator: must be connected to ring through a capacitor. Buzzer Output for line monitoring function: enabled by software setting. Digital Isolation Interface to ALIS-A: Must be connected to pin A21 of ALIS-A (see Chapter 3.3.5) Digital Isolation Interface to ALIS-A: Must be connected to pin A22 of ALIS-A (see Chapter 3.3.5) Digital Isolation Interface to ALIS-A: Must be connected to pin B21 of ALIS-A (see Chapter 3.3.5) Digital Isolation Interface to ALIS-A: Must be connected to pin B22 of ALIS-A (see Chapter 3.3.5) Digital Isolation Interface to ALIS-A: Must be connected to pin C21 of ALIS-A (see Chapter 3.3.5) Digital Isolation Interface to ALIS-A: Must be connected to pin C22 of ALIS-A (see Chapter 3.3.5) General Purpose Output Can be used, for example, for hook switch control. Disconnect if not in use. General Purpose Input/Output Default: Input. Tie to high or low if not in use. CID_R 5 I BUZZER 9 O A11 28 O A12 1 O B11 2 I B12 3 I C11 26 O C12 27 O GPO_D 22 O GPIO_D 8 I/O Preliminary Data Sheet 20 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Functional Description 3 Functional Description The ALIS chipset provides all the major parts of a conventional front-end for modem solutions. This section describes that functionality. Since adaptability to different countries' line characteristics is a particular feature of the ALIS chipset, this section also describes how that adaptation is implemented in a Digital Filter Structure (DFS). 3.1 Functional Overview The ALIS provides a codec and an electronic Data Access Arrangement (DAA). Advanced features such as ring detection, DTMF and pulse dialing, and Caller-ID are integrated on-chip. Operating states such as Idle and Sleep are implemented to minimize power consumption. 3.2 Block Diagram Received modem data passes from the Tip/Ring of the telephone interface to the analog front-end ALIS-A, where it is digitized and passed through an digital isolation interface to the ALIS-D. The data proceeds through a sequence of hardware and digital filters and then to the Serial Data Interface (SDI) to the data pump. Transmitted modem data traverses this path in the reverse direction. Caller-ID data are also provided by the Tip/Ring, but received at the ALIS-D, in the Caller-ID Functions block. The signal is converted to a 1-bit data stream, passed to the Hardware Filter block for down-sampling, and further passed to the DFS for bandpass filtering and Hilbert transforms, in order to decode it. It is stored in the CID-RAM. Ring detection is performed in the DFS, based on the analog signal received at the ALISA and passed through the ADC and Hardware Filters. This signal is filtered, integrated and compared to a threshold to determine if a potential ring is valid. Control information from the Host is provided to the ALIS-D through the Serial Control Interface (SCI). This includes both operational commands and programming commands. General purpose control is provided for both the ALIS-A and ALIS-D. The ALIS-D also provides the SLEEP output signal to indicate that it is in Sleep state, and the BUZZER output signal for line monitoring. * Preliminary Data Sheet 21 04.99 * Figure 3-1 Preliminary Data Sheet Transmit/Receive Control Data BUZZER Serial Control Interface (SCI) Control Digital Isolation GPIO ALIS Block Diagram GPIO Coefficent RAM (CRAM) A/D Digital Filter Structure (DFS) HW Filter Interface SLEEP Control 22 Caller-IDStorage RAM Serial Data Interface (SDI) Caller-ID Functions ALIS-A PSB 4595 Transmit/Receive Modem Data MCLK Tip/Ring Hybrid and Filters External Crystal or Master Clock D/A Clocking ALIS-D PSB 4596 VDDA Control PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Functional Description 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Functional Description 3.3 3.3.1 Functional Blocks Control: ALIS-A Provides general purpose input/output. This employs pins GPI_0_A, GPI_1_A, GPO_0_A, and GPO_1Q_A. 3.3.2 VDDA Control Generates the supply voltage for the ALIS-A from the Tip/Ring voltage. 3.3.3 Hybrid Circuit and Filters The hybrid circuit provides two-wire to four-wire conversion, while analog anti-aliasing pre-filters and smoothing post-filters condition the modem data. 3.3.4 Analog/Digital Conversion Analog-to-Digital Conversion (ADC) for received data and Digital-to-Analog Conversion (DAC) for transmitted data are provided by high-performance oversampling. This deltasigma technique converts the analog signal to a digital one-bit data stream. 3.3.5 Digital Isolation Interface The digital isolation interface is further described in Chapter 5.1.5. 3.3.6 Caller-ID Functions The FSK Caller-ID signal is converted to a 1-bit data stream to reduce power consumption, and then passed to the Hardware Filter block. The Caller-ID interface is further described in Chapter 5.1.4. 3.3.7 Hardware Filters The hardware filters provide interpolation and decimation functions for both modem data and Caller-ID data. 3.3.8 Digital Filter Structure The Digital Filter Structure (DFS) implements the functions of line impedance matching, bandpass filtering, Hilbert transforms, channel equalization, sampling, ring detection, and Caller-ID storage through Digital Dignal Processing (DSP) algorithms. The specific performance of the DFS is matched to a particular country's line characteristics by the values of parameters and coefficients stored in the Coefficient RAM (CRAM) on-chip. Preliminary Data Sheet 23 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Functional Description 3.3.9 Serial Control Interface The SCI is further described in Chapter 5.1.1.1. 3.3.10 Serial Data Interface The SDI is further described in Chapter 5.1.1.2. 3.3.11 Control: ALIS-D Provides general purpose input/output. This employs pins GPO_D and GPIO_D. 3.3.12 BUZZER The output to BUZZER is the one bit digital data stream received from the ALIS-A over the digital isolation interface. Preliminary Data Sheet 24 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Functional Description 3.3.13 * Clocking FMCLK = 24.576 MHz Default: FMCLK / Finternal = 1.5 (K = 0) Finternal = 16.384 MHz fac_fsc Divider 00 : 2048 01 : 1024 10 : 512 fac_sdi Divider 010 : 8 011 : 16 100 : 32 101 : 64 FSC frequency = 8 kHz, 16 kHz, 32 kHz SDI_CLK = 2.048 MHz, 1.024 MHz, 512 kHz, 256 kHz fac_os 8 kHz 00 SDI_RX 16 kHz 01 32 kHz 10 Sampling frequency= 8 kHz 16 kHz 32 kHz SDI_TX 8 kHz 00 16 kHz 01 32 kHz 10 Figure 3-2 Clocking of the ALIS in Master Mode All operating frequencies of the ALIS are derived from an external source MCLK, an external crystal or master clock. To allow flexibility in selection of external frequency, while enforcing strict integer ratios among the operating frequencies, an internal clock is derived as an adjustable reduction from the external source; and all other rates are derived through reduction of the internal clock by powers of 2. Figure 3-2 shows the relationship among these frequencies in Master Mode (see Chapter 3.4.2), as well as the options. Four programmable parameters are available: the internal clock parameter K, the framesync reduction parameter fac_fsc, the data clock reduction parameter fac_sdi, and the oversampling parameter fac_os. Preliminary Data Sheet 25 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Functional Description The internal clock frequency Finternal is reduced from the external clock frequency FMCLK by a factor which depends on the parameter K according to the equation: F F MCLK = ---------------------------------------------internal ) ( 32768 + K - 1 + ------------------------------ 2 x 32768 F MCLK K = 65536 x ------------------------- - 1 - 32768 F internal or K is an integer value in the range from -32768 to 32767. The sampling rate for the analog data is is obtained by dividing the internal clock frequency by 512, 1024, or 2048. In Master Mode, the framesync frequency is obtained by dividing the internal clock frequency by 512, 1024, or 2048; and the data clock (SDI_CLK) frequency is obtained by dividing the internal clock frequency by 8, 16, 32 or 64. In the figure, the reduction factors are exact, but the specific frequencies depend on K and the source frequency. * FMCLK = 24.576 MHz FSC = 8 kHz FMCLK / Finternal = 1.5 Finternal = 16.384 MHz fac_os 8 kHz 00 SDI_RX 16 kHz 01 32 kHz 10 Sampling frequency = 8 kHz 16 kHz 32 kHz SDI_TX 8 kHz 00 16 kHz 01 32 kHz 10 Note: Numbers are valid for FSC = 8 kHz Figure 3-3 Clocking of the ALIS in Slave Mode Preliminary Data Sheet 26 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Functional Description In the Slave Mode, the ALIS receives both SDI_CLK and the framesync frequency from an external device. The internal clock is still controlled by the external source (MCLK) and the K parameter, but in this case the value of K is set by a phase-locked loop synchronized to the externally generated framesync. Other frequencies are still driven by the internal clock. See Figure 3-3. In either Mode, the framesync frequency and the sampling frequency have the same range: if they are set equal, each frame will have one sample. If the sampling frequency exceeds the framesync frequency, multiple samples will be included in each frame. It is important to select fac_fsc and fac_os so that the framesync frequency does not exceed the sampling frequency. Comparison of the framesync and data clock rates shows that the number of SDI_CLK cycles per frame is the ratio of the division factor determined by fac_fsc to the division factor determined by fac_sdi: this is always a multiple of 32. When cascading multiple devices (see Chapter 5.1.1.5 and Chapter 5.1.1.7), the fac_fsc and fac_sdi parameters must be set appropriately. 3.4 Operating Modes There are four distinct ways in which the ALIS-D Host interface can be configured. They are characterized by selection of the mode of the Host interface, and by the independent selection of the source of clocking and frame synchronization. 3.4.1 Multiplex and Non-Multiplex Modes The Host interface can be provided by two different modes. In the Multiplex Mode, the SCI and the SDI are provided over a single set of pins; in the Non-multiplex Mode, the SCI and SDI are provided over separate sets of pins. 3.4.2 Master and Slave Modes The ALIS-D can operate in two different modes. In the Master Mode, clocking and frame synchronization are generated by the ALIS-D; in the Slave Mode, they are provided by the Host. This has been discussed in Chapter 3.3.13. Preliminary Data Sheet 27 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Operational Description 4 4.1 Operational Description Operational Overview The ALIS is initiated by a Reset, after which it undergoes programming by the Host to determine its configuration. The ALIS chipset can be set to implement the following features: * Auto Sleep: The chipset will transition automatically from Idle state to Sleep state after a programmable timeout (see register R4). * Non-Automatic Call Processing: If Automatic Call Processing is not activated, the chipset will transition from one state to another only under the direct command of the Host. * Automatic Call Processing: the ALIS will respond to incoming ringing on the Tip/Ring by transitioning among the operating states defined in Chapter 4.2. Within the Automatic Call Processing feature, it is possible to set the Caller-ID feature, which will allow automatic storage of the Caller-ID signal; and to instruct the ALIS to issue an interrupt at a programmable number of rings. 4.2 Operating States The following chapter describes the different operating states controlled by STATE register R3. 4.2.1 Idle State In Idle state, the SCI function is active (Multiplex Mode and None-Multiplex Mode). The Host can read the Caller-ID storage RAM to capture the Caller-ID information, and access the CRAM to program the ALIS-D by loading or reading coefficients. In Idle state, modem data for transmit from the data pump are ignored. 4.2.2 Ringing State In the Ringing state, the ALIS-D chip is prepared to detect a valid ring. A ringing burst is determined to be valid if it matches the frequency and level appropriate to the country for which the ALIS-D is set. 4.2.3 Caller-ID State In the Caller-ID state, incoming Caller-ID information will be stored in the Caller-ID storage RAM. Preliminary Data Sheet 28 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Operational Description 4.2.4 Conversation State In Conversation state, the SDI is active. The ALIS chipset can receive and transmit modem data, and the tone generators are available. The ALIS synthesizes the DC and AC characteristics of the DAA only in this state. 4.2.5 Pulse Dialing State In Pulse Dialing state, the Host can perform pulse dialing by switching the bit pdial in register R11. 4.2.6 Sleep State In Sleep state, power consumption by the ALIS is minimized. All internal clocks are turned off. If the ALIS-D uses an external crystal for the master clock, it is also turned off. If instead, it is receiving an external master clock, this can now be turned off safely. The SLEEP pin indicates high in this state. The ALIS-D can be awakened from the Sleep state by toggling on the SDI_TX; or when ringing on the Tip/Ring stimulates the ALIS-A: the external master clock (if present) must be turned on; and the SLEEP pin transits to low. The internal clock is switched on automatically. Alternatively, it can also be Reset using the RESET pin, as described in Chapter 5.3. 4.3 Operational Performance Telephone line characteristics differ from country to country. However, the table below summarizes what the ALIS can do, as a DAA, in any one country, when loaded with the appropriate set of parameters and coefficients. These coefficient sets are available from Infineon Technologies. Table 4-1 Parameter DAA Performance Parameters Symbol Test Condition High-Pass Filter On High-Pass Filter Off -0.125 0 Limit Values min. Frequency Response, FRT Transmit: Low -3 dB corner Frequency Response, FRT Transmit: Low -3 dB corner Frequency Response, Transmit: 300 - 3000 Hz Frequency Response, Transmit: 3400 Hz typ. max. 40 15 Hz Hz Unit FRT FRT 0.125 dB 0.125 0.650 dB Preliminary Data Sheet 29 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Operational Description Table 4-1 Parameter Transmit Full Scale Level: 0 dB gain Frequency Response, Receive: Low -3 dB corner Frequency Response, Receive: Low -3 dB corner Frequency Response, Receive: 300 to 3000 Hz Frequency Response, Receive: 3400 Hz Receive Full Scale Level: 0 dB gain Total Harmonic Distortion plus Noise: C-weighted DAA Performance Parameters (cont'd) Symbol Test Condition Limit Values min. typ. 3 160 28 -0.125 0 between Tip and Ring 1 kHz, -10 dBm0 1 kHz, -10 dBm0 74 max. dBm Hz Hz Unit VTX FRR FRR FRR FRR VRX HDN between Tip and Ring High-Pass Filter On High-Pass Filter Off 0.125 dB 0.125 0.650 dB 0 77 dBm dB Full Scale dBFS dB 35 340 400 dB s s Total Harmonic Distortion HDN plus Noise: linear-weighted Return Loss: 300 - 3400 Hz Transhybrid Loss: 300 to 3400 Hz Group Delay, Receive Group Delay, Transmit THL DRA DXA 72 16 27 75 Preliminary Data Sheet 30 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Operational Description Figure 4-1 shows the Group Delay Distortion, relative to TGmin at 1.5 kHz. This graph applies to the case that the high-pass filter is switched on. If it is off, the distortion will be less, but the exact behavior depends on external components. * $ 6 7* # " ! '$ $AA% $ !$AA!%AAA!' "$ )UHTXHQF\ N+= Figure 4-1 Group Delay Distortion, Transmit and Receive (High-Pass Filter On) Figure 4-2 shows the suppression of the digital output of an out-of-band 0 dBm sine wave applied to the analog input, compared to the digital output of a reference in-band (1 kHz) 0 dBm sine wave. * $WWHQXDWLRQ G% )UHTXHQF\ N+= Figure 4-2 Out-of-Band Receive (High-Pass Filter On) 31 04.99 Preliminary Data Sheet PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Operational Description * $WWHQXDWLRQ G% )UHTXHQF\ N+= Figure 4-3 Out-of-Band Transmit Figure 4-3 shows the suppression of the out-of-band analog output of any in-band signal (300 - 3990 Hz), compared to the analog output of a reference in-band (1 kHz) 0 dBm0 sine wave. Preliminary Data Sheet 32 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description 5 Interface Description The ALIS has interfaces for data and control from the Host, for access to the telephone network, and for incoming Caller-ID signals. In addition, the ALIS-D must be connected to an external clock or crystal. 5.1 5.1.1 Hardware Interface Host Interface: Control and Data The Host interface has two principal components: the Serial Control Interface (SCI) and the Serial Data Interface (SDI). The Host uses the SCI to issue operational commands to the ALIS-D and to read from and write to its registers. ALIS-D is also programmed with this interface. The SDI transports modem data between the Host and the ALIS-D. The SCI and the SDI can use separate pins of the ALIS-D, or they can share pins, using different time slots. We denote the first case as the Non-multiplex Mode of the Host Interface, and the second as the Multiplex Mode. In this section, we describe the functions and signals of the SCI and SDI, and how they are mapped to the physical pin symbols of the ALIS-D in both Multiplex and Nonmultiplex Modes. We also describe how multiple ALIS chipsets can be cascaded. 5.1.1.1 Table 5-1 Serial Control Interface Mapping of SCI Signals to ALIS-D Pin Symbols Pin Symbol: Non- Pin Symbol: multiplex Mode Multiplex Mode INT SCI_CLK INT SDI_CLK SDI_TX SDI_RX FSC The SCI has the following signals: Serial Control Interface (SCI) Signal Interrupt: to Host (active low). Clocking 8-bit Commands, 8-bit Write contents: from SCI_IN Host. 8-bit Read contents: to Host. Interface Synchronisation SCI_OUT SCI_CS/SWAP Write bits from the Host are latched on the falling edge of the Clocking, Read bits to the Host are changed on the rising edge of the SCI_CLK. Preliminary Data Sheet 33 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description 5.1.1.2 Table 5-2 Serial Data Interface Mapping of SDI Signals to ALIS-D Pin Symbols Pin Symbol: Non- Pin Symbol: multiplex Mode Multiplex Mode FSC SDI_CLK SDI_TX SDI_RX FSC SDI_CLK SDI_TX SDI_RX The SDI has the following signals: Serial Data Interface (SDI) Signal Frame Synchronization Data Clock for Modem 16-bit Transmit data: from data pump. 16-bit Receive data: to data pump. The SDI is a synchronous interface: the FSC pulse identifies the beginning of a frame, Write bits from the Host are latched on the falling edge of the SDI_CLK, and Read bits to the Host are changed on the rising edge of the SDI_CLK. 5.1.1.3 Master/Slave Modes: The ALIS-D can be operated either as a master or slave device, controlled by the BM pin. Table 5-3 Symbol SDI_CLK FSC Master/Slave Modes of ALIS-D: SDI Roles ALIS-D as Master (BM = high) Frame Synchronization is generated by ALIS-D. ALIS-D as Slave (BM = low) Frame Synchronization is generated by Host. Data Clock is generated by ALIS-D. Data Clock is generated by Host. In Master Mode, the ALIS-D begins a data frame with the rising edge of the FSC, which coincides with a rising edge of SDI_CLK. The next rising edge of SDI_CLK indicates the start of the first bit for SDI_RX (Receive data); at the first subsequent falling edge of SDI_CLK, the first bit for SDI_TX (Transmit data) is latched. When not active, the SDI_RX pin is in tristate condition (internal switchable pull-up). Preliminary Data Sheet 34 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description * 6GDT9 QT7A#$(% C 9hhAQ SDI_CLK FSC SDI_TX SDI_RX SDI VDD BM Figure 5-1 * SDI in Master Mode SDI_CLK FSC SDI_TX SDI_RX Figure 5-2 SDI Framing in Master Mode In Slave Mode, it is required that the Host produce the Frame Synchronization synchronously with the Data Clock. The ALIS-D detects the start of a data frame when the FSC is high at the falling edge of SDI_CLK. The next rising edge of SDI_CLK indicates the start of the first bit for SDI_RX (Receive data); at the first subsequent falling edge of SDI_CLK, the first bit for SDI_TX (Transmit data) is latched. When not activated, the SDI_RX pin is in tristate condition (internal switchable pull-up). Preliminary Data Sheet 35 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description * $/,6' 36% +RVW 'DWD 3XPS SDI_CLK FSC SDI_TX SDI_RX SDI BM GND Figure 5-3 * SDI in Slave Mode SDI_CLK FSC SDI_TX SDI_RX Figure 5-4 SDI Framing in Slave Mode Preliminary Data Sheet 36 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description 5.1.1.4 Multiplex Mode The Host Interface is set in this mode when the SCI_CLK/MODE pin of ALIS-D is set to high during Reset. In Multiplex Mode, five pins are shared by the Serial Data Interface (SDI) and the Serial Control Interface (SCI). The interfaces have different time slots. Table 5-4 INT SDI_CLK SDI_TX SDI_RX FSC * Multiplex Mode Pins SDI Signal n/a SDI_CLK SDI_TX SDI_RX FSC SCI Signal INT SCI_CLK SCI_IN SCI_OUT n/a Physical Pin Label $/,6' 36% INT +RVW 'DWD 3XPS SDI_CLK FSC SDI_TX SDI_RX Physical SDI FSC2 Figure 5-5 ALIS-D in Multiplex Mode The following figures show the time slots for the SCI and SDI bits. When the SCI_CS/ SWAP pin is set to low, the SDI is assigned to the first 16 bits after the FSC, and the SCI is assigned to the next 16 bits. When active, the SDI receives and transmits modem data continually. By contrast, the SCI is used only when the Host needs it: during a Write command, the Host uses only the SCI_IN signal for the command and the content of that command; but during a Read command, the SCI_IN signal (on the SDI_TX pin) is used to request the Read (of a register), and the SCI_OUT signal (on the SDI_RX pin) is used for the actual contents. If the SCI is not used it is recommended to send zeros in the command slot. Figure 5-6 and Figure 5-7 also show a second communication slot for a second device: this will be discussed in Chapter 5.1.1.5. Preliminary Data Sheet 37 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description * SDI SCI 2nd Communication Slot for 2nd Device SDI_RX SDI_TX FSC SDI_CLK 16-Bit Modem Data 16-Bit Modem Data 8 Bit CMD 8 Bit Contents Figure 5-6 * Multiplex Mode (SWAP ='0'): Write Access SDI SCI 2nd Communication Slot for 2nd Device SDI_RX SDI_TX FSC SDI_CLK 16-Bit Modem Data 16-Bit Modem Data 8 Bit CMD 8 Bit Contents Figure 5-7 Multiplex Mode (SWAP ='0'): Read Access When the SWAP pin is set to high, the ordering of the SCI and SDI is reversed: the first 16 bits after the FSC are for the SCI, and the next 16 bits are for the SDI (see Figure 58). Preliminary Data Sheet 38 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description * SCI SDI 2nd Communication Slot for 2nd Device SDI_RX SDI_TX FSC SDI_CLK 8-Bit CMD 8-Bit Contents 16-Bit Modem Data 16-Bit Modem Data Figure 5-8 Multiplex Mode (SWAP = '1'): Write Access Within the context of the Multiplex Mode, the ALIS-D still can operate as either a Master or a Slave device, as described in Chapter 5.1.1.2. 5.1.1.5 Multiplex Mode with Cascaded Devices The ALIS-D in Multiplex Mode can support an additional device, e.g., a codec for a speakerphone application. This device must be configured to receive synchronization from the FSC2 of the ALIS-D. The ALIS-D may be in Master Mode or in Slave Mode. As shown in Figure 5-9, the FSC input of the codec is connected to FSC2 output of the ALIS-D. The FSC2 signal is active high, one SDI_CLK cycle in duration. The delay between the FSC of the ALIS-D and the FSC2 must be set by programming to allow the codec to use the second communication slot. It can be be delayed from 0 to 63 cycles. This second slot is shown in more detail in Figure 5-10. Preliminary Data Sheet 39 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description * Digital Isolation Interface SDI_CLK FSC SDI_TX SDI_RX INT RESET ALIS-D PSB 4596 FSC2 delayed from FSC ALIS-A PSB 4595 7LS5LQJ Host (Data Pump) FSC2 FSC RESET SDI_RX SDI_TX SDI_CLK 2nd Codec Figure 5-9 * * ALIS-D in Multiplex/Master Mode with an Additional Codec ALIS-D Audio Codec SDI_RX SDI_TX FSC SDI_CLK FSC2 16 Bit Modem Data 1 16 Bit Modem Data 1 CMD 1 Contents 1 16 Bit Modem Data 2 16 Bit Modem Data 2 CMD 2 Contents 2 Figure 5-10 Framing for an Additional Codec: Read Access The role of the second device can also be performed by a second ALIS chipset, with the second ALIS-D in Multiplex/Slave Mode. This is shown in Figure 5-11 and Figure 5-12. Note in Figure 5-11 that the INT pins can share a common input to the Host, or have separate inputs. Preliminary Data Sheet 40 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description * SDI_CLK FSC SDI_TX SDI_RX INT RESET FSC2 FSC2 delayed from FSC ALIS-D PSB 4596 ALIS-A PSB 4595 7LS5LQJ Host (Data Pump) FSC RESET SDI_RX SDI_TX SDI_CLK INT Digital Isolation Interface ALIS-D PSB 4596 FSC is input BM pin = low ALIS-A PSB 4595 7LS5LQJ Figure 5-11 Dual-Line Modem: Two ALIS Chipsets * 1st ALIS-D 2nd ALIS-D (Slave Mode) SDI_RX SDI_TX FSC SDI_CLK FSC2 16 Bit Modem Data 1 16 Bit Modem Data 1 CMD 1 Contents 1 16 Bit Modem Data 2 16 Bit Modem Data 2 CMD 2 Contents 2 Figure 5-12 Framing for Two ALIS-D Chips: Read Access It is possible to further cascade more ALIS-Ds "piggy-back", within the limitation that each receives 32 bits per frame. This is controlled by properly selecting the sub-dividing parameters which determine the SDI clock-rate and the sampling (FSC) rate as shown in Figure 3-2. Preliminary Data Sheet 41 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description 5.1.1.6 Non-multiplex Mode Figure 5-13 shows the physical layout of the Non-multiplex Mode. The SDI is shown as configured for the ALIS-D acting as a Master device (see Table 5-3). * 6GDT9 QT7A#$(% Hvppyyr SCI_CLK SCI_CS SCI_IN SCI_OUT INT SCI SDI_CLK FSC C 9hhAQ SDI_TX SDI_RX FSC2 SDI Figure 5-13 ALIS-D in Non-multiplex/Master Mode In Non-multiplex Mode, the SCI_CLK is not synchronous: this is illustrated in Figure 514 and Figure 5-15, which show the framing for reading and writing to the SCI in this mode. * SCI_IN SCI_OUT SCI_CS SCI_CLK CMD Contents Figure 5-14 Framing for Read Access to SCI in Non-multiplex Mode During execution of a Read command, the ALIS-D will not accept new commands on SCI_IN. However, this can be interrupted by setting SCI_CS high. Because SCI_OUT goes to high-impedance (tristate) during the last half-clock-cycle of a Read, it is possible to strap SCI_OUT together with SCI_IN to a bi-directional data pin on the Host, without causing bus contention. This can be used to reduce the number of pins to the microprocessor. Preliminary Data Sheet 42 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description * SCI_IN SCI_OUT SCI_CS SCI_CLK CMD Contents Figure 5-15 Framing for Write Access to SCI in Non-multiplex Mode 5.1.1.7 Multiple ALIS Chipsets in Non-multiplex Mode In the Non-multiplex Mode, the SCI and the SDI are physically separate, so it is possible to cascade them separately. Figure 5-13 shows one ALIS-D interfaced to a Host; however, it would be possible for multiple ALIS-Ds to share all SCI lines except for the SCI_CS. As long as each chipset has its own chip select pin on the Host, it can be addressed individually. Similarly, several chipsets could share the SDI lines to the Data Pump. With a layout similar to Figure 5-11 but in Non-multiplex Mode, and with all ALIS-Ds after the first in Slave Mode, each chipset can be given its own 16-bit time slot. This would look similar to Figure 5-12, except that there would be no SCI time slots, so each chipset needs only 16 bits per frame instead of 32. 5.1.2 5.1.2.1 Master Clock External Clock The ALIS-D can be driven by an external clock of frequency between 24 MHz and 33 MHz. This is connected to pin MCLK1; MCLK2 is then left unconnected. 5.1.2.2 External Crystal Alternatively, the ALIS-D can be driven by an external crystal of a fundamental frequency between 24 and 33 MHz. This is connected between pins MCLK1 and MCLK2. Preliminary Data Sheet 43 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description 5.1.3 * Telephone Line Interface VDDA R5 SENS VDD C7 T2 T2G R7 C5 Tip C4 R6 TIP-AC D1 D2 D5 TIP R4 T1 R3 D3 D4 D6 C6 T1G R2 Ring R1 C3 RING-AC RING C2 VREF GNDA CAP1 C1 CAP2 Figure 5-16 Connection of ALIS-A to Telephone Line Table 5-5 Transistors T1 External Components PSB 4595 Type/Value BSP 88 Tolerances Comments FET, N channel enhancement type FET, N channel depletion type Tolerances Comments 1% 5% T2 Resistors R1 R2 BSP 129 Type/Value 36 4.7 Preliminary Data Sheet 44 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description Table 5-5 R3 R4 R5 R6 R7 Capacitors C1 C2 C3 C4 C5 C6 C7 Diodes D1 D2 D3 D4 D5 D6 External Components PSB 4595 (cont'd) 24 k 470 k 3.6 1k 240 Type/Value 1/6V 15 n / 6 V 22 n / 250 V 22 n / 250 V 22 / 6 V 0.68 n / 250 V 1 / 250V Type/Value 1/2 BAW101 1/2 BAW101 1/2 BAW240A 1/2 BAW240A 1/2 BAW240A 1/2 BAW240A Tolerances Comments 10 % 10 % 10 % 10 % 20 % 5% 10 % Tolerances Comments 1% 1% 5% Figure 5-16 shows the external components required to connect the ALIS-A to the telephone line. Component values shown are typical. Transistor T1 modulates the loop current and synthesizes the impedance. Transistor T2 regulates the supply voltage. Near Tip, note the relay that serves as hook switch. 5.1.3.1 DC Termination The interface to the Tip/Ring must match different characteristics in different countries. For example, the voltage/current relationship must fit inside a mask defined for that country, as shown in Figure 5-17. The voltage/current relationship for the ALIS-A Tip/ Ring interface is programmable, so that it can meet different masks when loaded with different coefficient sets. Full coefficient sets will be provided by Infineon Technologies, specific to each country; however, certain specific parameters are made available to allow exploration of the ALIS's flexibility with regard to the mask. The voltage/current relationship is governed by the equation: Preliminary Data Sheet 45 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description I ( V ) = ( V - V0 ) --------------------R and * for ( 9 - 9 ) 5 ,PD[ I ( V ) = Imax * for ( V - V0 ) R Imax In this equation, I is the line current, V is the voltage between Tip and Ring, and the following parameters are set by programming: R, the resistive slope: can be set to 100, 200, 240, or 280 . Imax, the maximum current: can be set to 50 or 100 mA. V0 is the sum of the forward voltages of the diodes in the external rectifying bridge (typically 2 * 0.4 V for Schottky diodes) plus the parameter DCO. DCO can be set to 0, 1.5, 3.5, or 7.2 V. Note: The DC termination is enabled only in the Conversation state. * 9ROWDJH 9 &XUUHQW $ Figure 5-17 Fitting Voltage/Current Relationship into Example Mask Preliminary Data Sheet 46 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description 5.1.3.2 Pulse Dialing Pulse dialing is possible by using the Pulse Dialing feature, and is accomplished by having the external transistor T1 short the tip and ring. The duration of and the interval between the pulses is controlled by the Host through the SCI by using the bit pdial in register R11. 5.1.3.3 DTMF Dialing DTMF tones are provided by two internal tone generators of frequency accuracy better than 1%. The absolute transmission level is programmable; but, the level of Tone Generator 2 is always 2 to 3 dB greater than that of Tone Generator 1 to realize the required emphasis. Therefore tone generator 2 should be used for the high frequency group of tones. Note: The tone generators can also generate in-band sine waves for test purposes. 5.1.3.4 Metering Pulses Metering pulses up to 2.5 VRMS can be sustained without degradation of performance. To prevent degradation in case of higher voltages, an external metering filter is required. 5.1.4 Caller-ID Interface The ALIS-D is connected to the Tip/Ring through capacitors by the CID_T and CID_R pins. The Caller-ID interface complies with the following specifications for Caller-ID: Bellcore TR-NWT-000030 and SR-TSV-002476, Bell 202, and ITU-T V.23. This service operates by transmitting the Calling Line Identification Presentation (CLIP) from the central office in the silent interval between the first and second rings, using 1200 baud FSK modulation. * 7LS5LQJ )LUVW 5LQJ )6. 0RGXODWLRQ CLIP 6HFRQG 5LQJ Channel Seizure Figure 5-18 Caller-ID Timing Mark State Preliminary Data Sheet 47 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description The ALIS-D can be programmed to detect line reversal, the method of initiating CallerID employed in the United Kingdom. )6. 0RGXODWLRQ CLIP /LQH 5HYHUVDO Channel Seizure Figure 5-19 Caller ID by Line Reversal The ALIS will detect the start of a Caller-ID signal after a MARK sequence (64 or more consecutive '1's), followed by a '0'. The ALIS will store the signal in the CID-RAM in the registers Index 64/Offset 0 to Index 88/Offset 15 (64 bytes). An interrupt can be generated when the last register is filled. Optionally, it is possible to operate in 2-page mode, in which case an interrupt is also generated when the register Index 72/Offset 15 is filled. The ALIS-D can store the signal in one of two formats: 1. Parsed according to ITU-T Recommendation V.14, with a START bit ('0'), 8 Caller-ID bytes (LSB first), and up to 10 STOP bits; or 2. Raw form: all bits after the MARK will be stored in order: Table 5-6 Index 64 ... 72 80 ... 88 Offset 0 ... 15 0 ... 15 7LS5LQJ )LUVW 5LQJ Mark State Storing the Caller ID Signal in CID-RAM Bit7 cid8 ... cid256 cid264 ... cid512 Bit6 cid7 ... cid255 cid263 ... cid511 Bit5 cid6 ... cid254 cid262 ... cid510 Bit4 cid5 ... cid253 cid261 ... cid509 Bit3 cid4 ... cid252 cid260 ... cid508 Bit2 cid3 ... cid251 cid258 ... cid507 Bit1 cid2 ... cid250 cid258 ... cid506 Bit0 cid1 ... cid249 cid257 ... cid505 i_cid2 i_cid1 (only in 2page mode ) Interrupt issued Note: see chapter "Programming" on page 7-78 on how to access these registers. Preliminary Data Sheet 48 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description 5.1.5 Digital Isolation Interface The isolation between ALIS-A and ALIS-D and therefore from the Tip/Ring side to the host/datapump side can be realized in two ways: Capacitive Interface Isolation is realized by six capacitances. The two "A", "B" and "C" capacitors must match to within 5 % of the selected value between 10 to 100 pF. * CAP_A1 A11 A12 CAP_A2 CAP_B1 A21 A22 B21 B22 CAP_B2 CAP_C1 B11 B12 C11 C12 CAP_C2 C21 C22 ALIS-D ALIS-A Figure 5-20 Isolation by Capacitive Interface Inductive Interface Isolation is realized by extra small transformers provided by third party. * A11 A12 B11 B12 C11 C12 A21 A22 B21 B22 C21 C22 ALIS-D ALIS-A Figure 5-21 Isolation by Inductive Interface Preliminary Data Sheet 49 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description 5.2 Software Interface The Host communicates with the ALIS chipset over the Serial Control Interface (SCI). There are three kinds of communication between them: * Programming of the ALIS-D (this is discussed in Chapter 7), * Operating commands (these control the real-time operation of the ALIS), and * Interrupts (there are seven specific interrupts that the ALIS-D uses; each can be separately disabled). All three types of communication entail either reading from or writing to registers in the ALIS-D. Preliminary Data Sheet 50 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Interface Description 5.3 Reset Sequence The ALIS-D can be Reset by a command from the Host, or by setting the RESET pin to low, and then releasing it. Over a period of 1300 clock-cycles of MCLK after the rising edge of RESET, the configuration registers are initialized to their default values: during this period, the ALIS-D undergoes mode selection: the MODE pin sets Multiplex (high) or Non-multiplex (low); the BM pin sets Master (high) or Slave (low). After that, the ALIS-D must be programmed by the Host to meet specific line conditions. This is done by using the ALIS-D programming commands to set the values of the parameters and coefficients in the Coefficient RAM (CRAM). Complete sets of coefficients appropriate for many countries are available from Infineon Technologies. After this Reset process, the ALIS-D is in Idle state. From that point on, it will transition to other states in accordance with operating commands from the Host and incoming signals from the Tip/Ring. Preliminary Data Sheet 51 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 6 Register Description The programming and much of the operation of the ALIS chipset is controlled by the values of bits in the registers of the ALIS-D. Some of these bits can be used to adapt the chipset to a specific application; whereas others are reserved for internal use. The ALIS-D registers are addressed by Index and Offset. Index values are incremented by 8, so the possible Index values are 0, 8, 16,...etc. Offset values are incremented by 1, so the possible Offset values are 0, 1, ... 15 (see "Programming" on page 7-78). Preliminary Data Sheet 52 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 6.1 Table 6-1 Register Map ALIS-D Registers Bit6 index(6) i_ring en_ring 0 to_sleep(6) n_ring(6) auto_ring Res. cad_to(6) cad_t(6) ring_cnt(6) 0 0 0 ver(6) Res. Index & MSB Offset Bit7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 index(7) i_cadence en_cadence gpo_d to_sleep(7) n_ring(7) auto_sleep Res. cad_to(7) cad_t(7) ring_cnt(7) 0 0 0 ver(7) Res. Bit5 index(5) i_cid2 en_cid2 0 to_sleep(5) n_ring(5) sdi_on Res. cad_to(5) cad_t(5) ring_cnt(5) 0 0 0 ver(5) Res. Bit4 index(4) i_cid1 en_cid1 0 to_sleep(4) n_ring(4) osci_on Res. cad_to(4) cad_t(4) ring_cnt(4) 0 0 0 ver(4) Res. Bit3 index(3) i_vdd en_vdd state(3) to_sleep(3) n_ring(3) ring_int Res. cad_to(3) cad_t(3) ring_cnt(3) 0 0 s_vdd ver(3) Res. Bit2 index(2) i_gpio_d en_gpio state(2) to_sleep(2) n_ring(2) line_rev Res. cad_to(2) cad_t(2) ring_cnt(2) 0 0 gpio_d ver(2) Res. Bit1 index(1) i_gpi_1_a en_gpi_1_a state(1) to_sleep(1) n_ring(1) cid_v14 Res. cad_to(1) cad_t(1) ring_cnt(1) 0 0 gpi_1_a ver(1) Res. LSB Bit0 index(0) i_gpi_0_a en_gpi_0_a state(0) to_sleep(0) n_ring(0) sdi_loop Res. cad_to(0) cad_t(0) ring_cnt(0) pdial valid_ring gpi_0_a ver(0) Res. Index 8/Offset 0 to Index 56/Offset 15 registers are used by the ALIS-D for internal processes. 8 ... 56 0 ... 15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Index 64/Offset 0 to Index 88/Offset 15 registers are used to store the Caller-ID information. 64 ... 88 0 ... 15 cid8 cid... cid512. cid7 cid... cid511 cid6 cid... cid510 cid5 cid... cid509 cid4 cid... cid508 cid4 cid... cid507 cid2 cid... cid506 cid1 cid... cid505 Index 96/Offset 0 to Index 96/Offset 5 registers are used by the ALIS--D for internal processes. 96 ... 96 96 96 0 ... 5 6 7 Res. Res. Res. k(7) k(15) Res. Res. Res. k(6) k(14) Res. Res. Res. k(5) k(13) Res. Res. Res. k(4) k(12) Res. Res. Res. k(3) k(11) Res. Res. Res. k(2) k(10) Res. Res. Res. k(1) k(9) Res. Res. Res. k(0) k(8) Index 96/Offset 8 to Index 104/Offset 2 registers are used by the ALIS--D for coefficients and parameters downloaded during initialization. Some of these bits, as identified, are also intended to allow adaptation for specific applications. 96 96 96 8 9 10 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. dco(1) Res. Res. dco(0) Res. Res. i_max Res. Res. r(1) Res. Res. r(0) Preliminary Data Sheet 53 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description Table 6-1 ALIS-D Registers (cont'd) Bit6 Res. Res. Res. Res. Res. Res. Res. Res. Index & MSB Offset Bit7 96 96 96 96 96 104 104 104 11 12 13 14 15 0 1 2 Res. Res. Res. Res. Res. Res. gpio_d_o en_fsc2 Bit5 Res. Res. Res. Res. Res. fac_fsc(1) Res. fsc2del(5) Bit4 gpo_1Q_a fac_os(1) Res. en_ptg2 en_cid fac_fsc(0) osc_off fsc2del(4) Bit3 gpo_0_a fac_os(0) Res. en_ptg1 Res. Res. sw_reset fsc2del(3) Bit2 Res. Res. Res. en_tg2 Res. fac_sdi(2) en_gpio_d_o Bit1 Res. Res. Res. en_tg1 Res. fac_sdi(1) Res. fsc2del(1) LSB Bit0 Res. Res. Res. Res. Res. fac_sdi(0) en_buzzer fsc2del(0) fsc2del(2) Index 104/Offset 3 to Index 112/Offset 3 registers are used by the ALIS-D for internal processing. 104 ... 112 112 3 ... 2 3 Res. Res. en_sci_pu Res. Res. Res. en_sdi_pu Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Index 128/Offset 0 to Index 184/Offset 15 registers are used to store the coefficients and parameters which adapt the behavior of the ALIS-D. Complete sets of coefficients and parameters are available from Infineon Technologies for each country. 128 ... 184 0 ... 15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Preliminary Data Sheet 54 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 6.2 Detailed Register Descriptions Register Description Example: Index Offset Short Name 7 6 Long Name Type Default Value 3* 2* 1 0 5 Res. 4 Bits marked with a "*" are set to 1 by default after reset. For this example, the default value would be 0CH. Reserved bits (like bit 5 in the example) are not allowed to be changed. Read-ModifyWrite commands are necessary. * 0 * 0 7 R0 6 INDEX 5 4 3 2 1 r/w 00H 0 index(7) index(6) index(5) index(4) index(3) index(2) index(1) index(0) * index[7:0] The ALIS-D registers are addressed by Index and Offset. Index values are incremented by 8, so the possible Index values are 0, 8, 16, ... etc. Offset values are incremented by 1, so the possible Offset values are 0, 1, ... 15. The use of this addressing scheme is described in Chapter 7, Programming. Preliminary Data Sheet 55 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 0 1 R1 INTERRUPTS r 00H 7 i_ cadence 6 i_ring 5 i_cid2 4 i_cid1 3 i_vdd 2 i_gpio_d 1 i_gpi_ 1_a 0 i_gpi_ 0_a Indicates which interrupt has caused high to low transition on INT line. All interrupts have time granularity of the FSC, faster events cannot be detected. A Read operation will reset this register to zero and will set the INT pin to inactive (high). * i_cadence Interrupt based on cadence time out. Two possible causes: * Valid ring not detected within cadence timeout (defined in register R8) after a valid ring. * The valid ring not detected within cadence timeout (defined in register R8) after a line reversal/spike. * i_ring Interrupt based on rings; three modes can be selected (see register R6). In each mode, the meaning of the interrupt is different: * If Automatic Call Processing not selected: A possible ring, as signal on Tip/Ring is higher than 10 VRMS. * Automatic Call Processing mode, ring_int = 1: A valid ring detect, interrupt every ring. * Automatic Call Processing mode, ring_int = 0: The programmed number (n_ring) of valid rings has been detected. * i_cid2 * Interrupt source: Caller-ID buffer is full or end of CID is detected. i_cid1 Interrupt source: First page of Caller-ID buffer is full or end of CID is detected (only active in 2-page mode). * i_vdd Interrupt source: Status change on power supply indicated by bit s_vdd in register R13. * i_gpio_d Interrupt source: Signal change on the pin GPIO_D on ALIS-D. Preliminary Data Sheet 56 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description * i_gpi_1_a Interrupt source: Signal change on the pin GPI_1_A on ALIS-A. * i_gpi_0_a Interrupt source: Signal change on the pin GPI_0_A on ALIS-A. Preliminary Data Sheet 57 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 0 * 2 7 R2 6 INTERRUPT ENABLE 5 en_cid2 4 en_cid1 3 2 1 r/w 00H 0 en_ en_ring cadence * en_vdd en_ gpio en_gpi_ en_gpi_ 1_a 0_a en_cadence Enable for cadence interrupt (i_cadence). en_cadence = 0 Disabled. en_cadence = 1 Enabled. * en_ring Enable for ring interrupt (i_ring). en_ring = 0 en_ring = 1 Disabled. Enabled. * en_cid2 Enable for interrupt at end of Caller-ID buffer (i_cid2). en_cid2 = 0 en_cid2 = 1 Disabled. Enabled. * en_cid1 Enable for interrupt for first page of Caller-ID buffer (i_cid1). en_cid1 = 0 en_cid1 = 1 Disabled. Enabled, 2-page mode enabled. * en_vdd Enable for i_vdd. en_vdd = 0 en_vdd = 1 Disabled. Enabled. * en_gpio Enable for i_gpio. en_gpio = 0 en_gpio = 1 Disabled. Enabled. Preliminary Data Sheet 58 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description * en_gpi_1_a Enable for i_gpi_1_a. en_gpi_1_a = 0 Disabled. en_gpi_1_a = 1 Enabled. * en_gpi_0_a Enable for i_gpi_0_a. en_gpi_0_a = 0 Disabled. en_gpi_o_a = 1 Enabled. Preliminary Data Sheet 59 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 0 * 3 7 gpo_d R3 6 0 STATE 5 0 4 0 3 state(3) 2 state(2) 1 r/w 00H 0 state(0) state(1) * gpo_d Value of gpo_d controls pin GPO_D. It is normally used to control the hook relay. gpo_d = 0 gpo_d = 1 Low on GPO_D. High on GPO_D. * state[3:0] IDLE CIDC RCMD CONV PULS SLEEP Operating states used to control ALIS functionality. 0000 0001 1000 1001 1010 1111 Idle state. Caller-ID state Ringing state. Conversation state. Pulse Dialing state. Sleep state. Other values of the variable state[3:0] are reserved. Preliminary Data Sheet 60 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 0 * 4 7* R4 6* SLEEP TIMEOUT 5* 4* 3* 2* 1* r/w FFH 0* Bit to_sleep to_sleep to_sleep to_sleep to_sleep to_sleep to_sleep to_sleep (7) (6) (5) (4) (3) (2) (1) (0) * to_sleep[7:0] Applicable only for Auto Sleep mode (see register R6): time (in FSC cycles), before device transitions to Sleep state. 0 * 5 7 R5 6 n_ring (6) RING NUMBER 5 n_ring (5) 4 n_ring (4) 3 n_ring (3) 2 n_ring (2) 1* r/w 02H 0 n_ring (0) Bit n_ring (7) * n_ring (1) n_ring[7:0] Applicable only for Automatic Call Processing mode (see register R6): number of rings before the ring interrupt (i_ring) will be set. Preliminary Data Sheet 61 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 0 * 6 7 R6 6 auto_ ring AUTO MODES 5 sdi_on 4 3 2 1* r/w 02H 0 sdi_loop Bit auto_ sleep * osci_on ring_int line_rev cid_v14 Sets the operating mode of the chip. auto_sleep Enables Auto Sleep mode for reduced power consumption. auto_sleep = 0 ALIS will remain in Idle state indefinitely. auto_sleep = 1 Sets Auto Sleep mode. Chip will transition automatically from Idle to Sleep state after timeout (register R4), if there is no activity on pin SDI_TX or on Tip/Ring. * auto_ring Enables the Automatic Call Processing mode. auto_ring = 0 auto_ring = 1 Automatic Call Processing mode not selected. ALIS set to Automatic Call Processing mode: The chip will accordingly set the following interrupts, if they are enabled: i_cid1, i_cid2 and i_ring. * sdi_on Enables automatic activation of the SDI. sdi_on = 0 sdi_on = 1 The SDI is activated only during Conversation state. The SDI is on except during Sleep state. * osci_on Enables automatic de-activation of the oscillator. osci_on = 0 osci_on = 1 During Sleep state, the oscillator is switched off. During Sleep state, the oscillator is active. Preliminary Data Sheet 62 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description * ring_int Applicable only in Automatic Call Processing mode: Enables counting of valid rings. ring_int = 0 ring_int = 1 Ring interrupt only after the programmed number of rings (n_ring). Every valid ring causes a ring interrupt (i_ring). * line_rev Applicable only if Automatic Call Processing is enabled: Enables automatic storing of Caller-ID signal after line reversal. line_rev = 0 line_rev = 1 No further action after line reversal. ALIS automatically starts to store Caller-ID after line reversal. * cid_ v14 Enables storing of Caller-ID data in V.14 format. cid_v14 = 0 cid_v14 = 1 Chip stores raw bits of the Caller-ID message to the CID-RAM. Chip stores Caller-ID message to the CID-RAM, according to ITU-T Recommendation V.14. * sdi_loop Test mode to check the SDI. sdi_loop = 0 sdi_loop = 1 Loop back is disabled. Data from Host are looped back through the SDI with a one-frame delay. Index 0/Offset 7 COUNTRY-SPECIFIC COEFFICIENTS WILL BE PROVIDED BY INFINEON TECHNOLOGIES. Preliminary Data Sheet 63 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 0 * 8 7 cad_to (7) R8 6* cad_to (6) CADENCE TIMEOUT 5* cad_to (5) 4* cad_to (4) 3* cad_to (3) 2* cad_to (2) 1 r/w 7DH 0* cad_to (0) Bit cad_to (1) * cad_to[7:0] The cadence timeout: the maximum period between two valid rings. The timeout is 500 * FSC period * cad_to[7:0]. For example, if the FSC frequency is 8000 Hz, the timeout period can be programmed to be a multiple of 500 * 1/8000 = 62.5 ms. 0 * 9 7 R9 6 CADENCE TIME 5 4 3 2 1 r 00H 0 Bit * cad_t(7) cad_t(6) cad_t(5) cad_t(4) cad_t(3) cad_t(2) cad_t(1) cad_t(0) cad_t[7:0] Time since last valid ring, measured in units of 500 FSC periods, just as for the cadence timeout (register R8). * Preliminary Data Sheet 64 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 0 * 10 7 R10 6 RING COUNT 5 4 3 2 1 r 00H 0 Bit ring_cnt ring_cnt ring_cnt ring_cnt ring_cnt ring_cnt ring_cnt ring_cnt (7) (6) (5) (4) (3) (2) (1) (0) * ring_cnt[7:0] Number of valid rings. Reset at the transition from Idle to Ringing state. 0 * 11 7 0 R11 6 0 PULSE DIALING 5 0 4 0 3 0 2 0 1 0 r/w 00H 0 pdial Bit * pdial Applicable only in Pulse Dialing state: this bit controls Make and Break for pulse dialing. pdial = 0 pdial = 1 Break Make 0 * 12 7 0 R12 6 0 RING STATUS 5 0 4 0 3 0 2 0 1 0 r 00H 0 valid_ ring Bit * valid_ring Indicates if the current ring is valid, as determined by frequency and amplitude. Updated every framesync. valid_ring = 0 valid_ring = 1 No ring, or no valid ring. Current ring valid. Preliminary Data Sheet 65 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 0 * 13 7 0 R13 6 0 INTERRUPT VALUES 5 0 4 0 3 s_vdd 2 gpio_d 1 r 00H 0 Bit * gpi_1_a gpi_0_a s_vdd Status of power supply in ALIS-A s_vdd = 0 s_vdd = 1 No power. Power is supplied and the digital isolation interface is running. gpio_d Value of GPIO_D pin. gpio_d = 0 gpio_d = 1 Low on GPIO_D. High on GPIO_D. gpi_1_a Value of GPI_1_A pin. gpi_1_a = 0 gpi_1_a = 1 Low on GPI_1_A. High on GPI_1_A. gpi_0_a Value of GPI_0_A pin. gpi_0_a = 0 gpi_0_a = 1 Low on GPI_0_A. High on GPI_0_A. Preliminary Data Sheet 66 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 0 * 14 7 R14 6 ver(6) VERSION 5 ver(5) 4 ver(4) 3 ver(3) 2 ver(2) 1 r 11H 0 ver(0) Bit * ver(7) * ver(1) ver[7:0] Version of the chip. Index 0/Offset 15 Index 56/Offset 15 RESERVED FOR INTERNAL USE, DO NOT MODIFY. * Index 64/Offset 0 Index 88/Offset 15 * CID-RAM: RESERVED FOR STORING THE CALLER-ID. * * * Index 96/Offset 0 Index 96/Offset 5 * RESERVED FOR INTERNAL USE, DO NOT MODIFY. Preliminary Data Sheet 67 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 96 Bit 6 7 k(7) R15 6 k(6) INTERNAL CLOCK PARAMETER 5 k(5) 4 k(4) 3 k(3) 2 k(2) r/w 1 k(1) 00H 0 k(0) 96 Bit 7 7 R16 6 k(14) INTERNAL CLOCK PARAMETER 5 k(13) 4 k(12) 3 k(11) 2 k(10) r/w 1 k(9) 00H 0 k(8) k(15) * k[15:0] All frequencies and rates of the chip derive from its internal clock Finternal (see Chapter 3.3.13). This is in turn derived from the external Master Clock FMCLK or an external crystal, as shown below. The reduction will be a factor FMCLK / Finternal between ~2 (K = 32767) and 1 (K = -32768). F ( 32768 + K ) MCLK -------------------------- = 1 + ------------------------------- 2 x 32768 F internal or F MCLK K = 65536 x ------------------------- - 1 - 32768 F internal K must programmed in complements of two. Table 6-2 K [Integer] -32768 ... -1 0 ... 32767 Programming Examples for K K [Hex] 8000 ... FFFF 0000 ... 7FFF FMCLK/Finternal [1] 1 ... ~ 1.5 1.5 ... ~2 Index 96/Offset 8 - 9 RESERVED FOR INTERNAL USE, DO NOT MODIFY. Preliminary Data Sheet 68 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 96 Bit 10 7 Res. R17 6 Res. DC Characteristics 5 Res. 4 dco(1) 3 dco(0) 2 i_max 1 r(1) r/w 00H 0 r(0) All bits in this register are provided by Infineon Technologies for country-specific application. However, the dco, i_max, and r bits are also made accessible to allow exploration of the ALIS's flexibility with regard to the DC termination (see Chapter 5.1.3.1). dco[1:0] DC voltage parameter DCO. 00 01 10 11 0V 1.5 V 3.5 V 7.2 V (in this case the resistive slope R = 70 regardless of bit r[1:0]) * i_max Maximum current Imax. 0 1 100 mA 50 mA * r[1:0] Resistive slope R. 00 01 10 11 280 240 200 100 Preliminary Data Sheet 69 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 96 * 11 7 Res. R18 6 Res. DIGITAL OUTPUTS 5 Res. 4 gpo_1Q _a 3 gpo_0 _a 2 Res. 1 r/w 00H 0 Res. Bit Res. * gpo_1Q_a Value of GPO_1Q_A pin. gpo_1Q_a = 0 gpo_1Q_a = 1 High on GPO_1Q_A. Low on GPO_1Q_A. gpo_0_a Value of GPO_0_A pin. gpo_0_a = 0 gpo_0_a = 1 Low on GPO_0_A. High on GPO_0_A. Preliminary Data Sheet 70 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 96 * 12 7 Res. R19 6 Res. OVERSAMPLING FACTOR 5 Res. 4 fac_os (1) 3 fac_os (0) 2 Res. 1 r/w 00H 0 Res. Bit Res. * fac_os[1:0] The value of fac_os determines the oversampling factor for the SDI (see Chapter 3.3.13): the sampling frequency is determined by: f OversamplingFactor = ----------------------------------------------------------- f internal 4096 sampling 00 01 10 11 Oversampling factor is 2. Oversampling factor is 4. Oversampling factor is 8. Not allowed. Index 96/Offset 13 * RESERVED FOR INTERNAL USE, DO NOT MODIFY. Preliminary Data Sheet 71 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 96 * 14 7 Res. R20 6 Res. DTMF 5 Res. 4 3 2 en_tg2 1 r/w 00H 0 Res. Bit * en_ptg2 en_ptg1 en_tg1 * en_ptg2 Enables Tone Generator 2 to use downloaded coefficients. en_ptg2 = 0 en_ptg2 = 1 Tone Generator 2 produces 1 kHz tone. Tone Generator 2 uses coefficients in CRAM. * en_ptg1 Enables Tone Generator 1 to use downloaded coefficients. en_ptg1 = 0 en_ptg1 = 1 Tone Generator 1 produces 1 kHz tone. Tone Generator 1 uses coefficients in CRAM. * en_tg2 Enables Tone Generator 2 en_tg2 = 0 en_tg2 = 1 Tone Generator 2 disabled. Tone Generator 2 enabled. * en_tg1 Enables Tone Generator 1 en_tg1 = 0 en_tg1 = 1 Tone Generator 1 disabled. Tone Generator 1 enabled. * * Preliminary Data Sheet 72 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 96 * 15 7 Res. R21 6 Res. ENABLE CID 5 Res. 4 en_cid 3 Res. 2 Res. 1 r/w 00H 0 Res. Bit * Res. en_cid Enables storage of the Caller-ID signal between the first two valid rings, or after line reversal. en_cid = 0 en_cid = 1 Caller-ID disabled. Caller-ID enabled. Preliminary Data Sheet 73 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 104 * 0 7 Res. R22 6* Res. FRAMESYNC 5 fac_fsc (1) 4 fac_fsc (0) 3 Res. 2 fac_sdi (2) 1* r/w 42H 0 fac_sdi (0) Bit fac_sdi (1) * * fac_fsc[1:0] The value of fac_fsc controls the framesync frequency (see Chapter 3.3.13): it determines the factor by which the frequency of the internal clock is divided to produce the framesync frequency (only in master mode). f internal f = ---------------------------FSC fscDivider 00 01 10 11 * FSC divider is 2048 (default). FSC divider is 1024. FSC divider is 512. Not allowed. fac_sdi[2:0] The value of fac_sdi controls the frequency of the SDI_CLK (see Chapter 3.3.13): it determines the factor by which the frequency of the internal clock is divided to produce the frequency of the SDI_CLK (only in master mode). f internal f = ---------------------------SDICLK sdiDivider 010 011 100 101 SDI_CLK divider is 8 (default). SDI_CLK divider is 16. SDI_CLK divider is 32. SDI_CLK divider is 64. Other values of the variable fac_sdi[2:0] are reserved. * Preliminary Data Sheet 74 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 104 * 1 7 R23 6 Res. Miscellaneous Control 5 Res. 4 osc_off 3 sw_ reset 2 en_gpio_ d_o 1 r/w 00H 0 en_ buzzer Bit gpio_ d_o * * Res. gpio_d_o Value for pin GPIO_D, if enabled as output. gpio_d_o = 0 gpio_d_o = 1 Low on GPIO_D. High on GPIO_D. osc_off Oscillator control osc_off = 0 osc_off = 1 Oscillator on: required when using crystal. Oscillator off: required when using external clock. * sw_reset Software Reset: sw_reset = 0 sw_reset = 1 Causes reset of ALIS. The chip is ready to respond again after 100 s. This bit is cleared automatically during the reset process. * en_gpio_d_o en_gpio_d_o = 0 en_gpio_d_o = 1 * GPIO_D as input. GPIO_D as output. en_buzzer Buzzer enable. en_buzzer = 0 en_buzzer = 1 BUZZER pin is set to low. BUZZER pin output is set to data stream after ADC. Preliminary Data Sheet 75 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description 104 * 2 7 R24 6 Res. FSC2 CONTROL 5 fsc2_ del(5) 4 fsc2_ del(4) 3 fsc2_ del(3) 2 fsc2_ del(2) 1 r/w 00H 0 fsc2_ del(0) Bit en_fsc2 * fsc2_ del(1) en_fsc2 Enables FSC2 as output. en_fsc2 = 0 en_fsc2 = 1 FSC2 pin is set permanent low. FSC2 is generated. * fsc2_del[5:0] Delay between FSC and FSC2. fsc2_del = 000000 fsc2_del = 000001 ... fsc2_del = 011111 fsc2_del = 111111 delay of one SDI_CLK cycle delay of two SDI_CLK cycles ... delay of 32 SDI_CLK cycles delay of 64 SDI_CLK cycles Index 104/Offset 3Index 112/Offset 1 RESERVED FOR INTERNAL USE, DO NOT MODIFY. Preliminary Data Sheet 76 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Register Description * 112 * 2 7 R25 6 en_ sdi_pu SDI_RX PULL-UP 5* Res. 4 Res. 3 Res. 2 Res. 1* r/w 23H 0* Res. Bit en_ sci_pu * Res. en_sci_pu Enables internal pull-up for SCI_OUT pin. en_sci_pu = 0 en_sci_pu = 1 Pull-up disabled. Pull-up enabled. * en_sdi_pu Enables internal pull-up for SDI_RX pin. en_sdi_pu = 0 en_sdi_pu = 1 Pull-up disabled. Pull-up enabled. Index 112/Offset 3 Index 112/Offset 15 RESERVED FOR INTERNAL USE, DO NOT MODIFY. Index 120/Offset 0 Index 120/Offset 15 RESERVED FOR INTERNAL USE, DO NOT MODIFY. Index 128/Offset 0 Index 184/Offset 15 COEFFICIENT RAM: COUNTRY-SPECIFIC COEFFICIENTS WILL BE PROVIDED BY INFINEON TECHNOLOGIES. Preliminary Data Sheet 77 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7 7.1 Programming Reset Sequence The Initialization of the ALIS V3 starts with either a software or a hardware reset: * Software Reset: The host sets the sw_reset bit (bit 3) in register R23 (see page 6-75) to 1. The sw_reset bit is automatically cleared to "0" during the reset process. * Hardware Reset: The RESET input pin (pin 23) of ALIS-D has to be set to "low" for at least 500 ns (see Chapter 8.2 on page 8-90). Important: It is not sufficient to detach the ALIS V3 from the power supply to initiate a Reset. Over a period of 1300 clock cycles (= duration of the initialization sequence) of the MCLK, after releasing the RESET, the configuration registers are set to their default values and the interface is configured according to the connection of the following pins during the reset phase: * pin 7 BM ("High" -> Master Mode / "Low" -> Slave Mode) and * pin 11 SCI_CLK/MODE ("High" -> Multiplex Mode / "Low" -> Non multiplex Mode) of the ALIS-D Note: If the Multiplex Mode is selected, the input SCI_CS/SWAP (pin 10) of the ALIS-D is used to select the order of SDI and SCI bits. Following this, * if in Master Mode: The host has to write the value of the internal clock parameter (K), and also the oversampling factor (fac_os), FSC dividing factor (fac_fsc), and SDI dividing factor (fas_sdi), when they are different from the default values (K = 0.5, fac_os = 2, fac_fsc = 2048 and fac_sdi = 8). * if in Slave Mode: K is automatically programmed according to the external sample rate FSC, However the host still has to program the oversampling factor (fac_os). After this Reset process, the configuration of the ALIS V3 is completed by writing all other required bits to the registers (please refer to "Configuration of the ALIS-D" on page 780). The ALIS V3 is in the Idle state, and from that point on a transition to other states in accordance with operating commands from the host and incoming signals from the Tip/ Ring is possible. Preliminary Data Sheet 78 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.2 Setup during Reset of the ALIS-D The following table shows as an example the order of events after resetting ALIS-D with - Serial Data Interface in Master mode - Serial Data Interface in Multiplex mode - First 16 bits SDI and next 16 bits SCI The order of the steps in this and the following tables is recommended for full functionality: * Table 7-1 Step Setup Sequence of the ALIS-D Logic State Description Reset Pin (Mode Setting) 23 "RESET" 7 "BM" 1) 1) 1 2 3 pin 23 = low pin 7 = high pin 11 = high Initiate Reset of ALIS-D ALIS-D is set in Master mode ALIS-D is set in Multiplex mode Master mode Multiplex mode 11 "SCI_CLK/ MODE"1) 10 "SCI_CS/ SWAP"1) 23 "RESET"1) Serial Data Interface 4 5 1) pin 10 = low pin 23 = high First 16 bits for SDI, next 16 bits for SCI Release of the Reset after tRESET,min (t.b.d., about 500 ns) see Table 2-2 on page 2-18 Preliminary Data Sheet 79 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.3 Configuration of the ALIS-D The following table shows the configuration of ALIS-D with - Fractional Divider (Parameter K) - FSC frequency and SDI Clock - Oversampling Factor * Table 7-2 Step Configuration Sequence of the ALIS-D1) Value2) (Example) 00h (default) 00h (default) XX01X100 Description Register Fractional Divider (Parameter K) 6 7 8 R15 (see page 6-68) R16 R22 (see page 6-73) R19 (see page 6-71) Configuration of the Fractional Divider (only in Master mode): Internal Clock = 16.384 MHz FSC frequency and SDI Clock FSC = 16 kHz (fac_fsc = 01b) and SDI_CLK = 512 kHz (fac_sdi = 100b) Sampling frequency = 16 kHz (fac_os = 01b for oversampling factor = 4) Oversampling factor 9 XXX01XXX 1) 2) valid for MCLK = 24.576 MHz X bits are not allowed to be changed (read-modify-write (r/w) operation required). Preliminary Data Sheet 80 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.4 Determination of the State of the ALIS-D The following table shows the determination of the State of the ALIS-D with - Automatic power mode switching - Detection of Caller-ID - Ring interrupt after two rings * Table 7-3 Step 10 Configuration Sequence of the ALIS-D Value1) 40h Description Enables the Automatic Call Processing mode Two rings are programmed before the ring interrupt will be set. If Auto Sleep mode is enabled go to sleep after 10 frames. Ring interrupt Enables the interrupts - Ring - CID 1, CID 2 - Cadence CRAM write CRAM registers are written according to the country specification Switch DSP flags XXX1100X Enables the Tone Generators using CRAM coefficients (en_ptg1 = 1, en_ptg2 = 1, en_tg1 = 0, en_tg2 = 0) Enables Caller-ID (en_cid = 1) Automatic Power mode switching Register R6 (see page 6-62) R5 (see page 6-61) R4 (see page 6-61) R2 (see page 6-58) 11 12 02h 0Ah 13 F0h 14 Coefficient registers (Index 128 - 184) R20 (see page 6-72) R21 (see page 6-73) 15 16 1) XXX1XXXX X bits are not allowed to be changed (read-modify-write (r/w) operation required). Preliminary Data Sheet 81 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.5 Commands Programming of ALIS-D consists of writing to or reading from registers of the ALIS-D: * A Read command allows the host to determine the contents of a register in the ALIS-D. It includes the address of the register to be read. * A Write command allows the host to set the contents of a register. It includes the address of the register to be set, and is followed by the data to be written into that register. Because of the extensive register space required, the address of a register is determined by two parts: - the 8-bit Index and - the 4-bit Offset. A Read or Write command requires either one or two steps, depending on the indexed addressing requirement. If the Index is 0, one step is required. If the Index is not 0, two steps are required. Preliminary Data Sheet 82 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.5.1 Single-Step Command If the Index for a register is 0 and the Offset A[3:0] is not 0, Read or Write Commands are executed as single step commands. The data to be written consists of the byte D[7:0]. 7.5.1.1 * Single-Step Write Command 7 Read/ Write 0 6 Index 0 5 Offset_ 3 A3 4 Offset_ 2 A2 3 Offset_ 1 A1 2 Offset_ 0 A0 1 Fixed 1 0 Don't Care x Bit * Data: Bit * 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 In the command byte, the MSB (bit 7) is 0 for Write; bit 6 is 0 because the Index is 0 (extended addressing is not needed); the Offset takes 4 bits (bit 5 to bit 2); the fixed bit 1 always has the value 1. The LSB (bit 0) is a dont care bit. Both command and data are transmitted at the SCI_IN input pin. 7.5.1.2 * Single-Step Read Command 7 Read/ Write 1 6 Index 0 5 Offset_ 3 A3 4 Offset_ 2 A2 3 Offset_ 1 A1 2 Offset_ 0 A0 1 Fixed 1 0 Don't Care x Bit * Data: Bit * 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 In the command byte, the MSB (bit 7) is 1 for Read; bit 6 is 0 because the Index is 0 (extended addressing is not needed); the Offset takes 4 bits (bit 5 to bit 2); the fixed bit 1 always has the value 1. The LSB (bit 0) is a dont care bit. The Read Command is transmitted at the SCI_IN input pin; the data of the addressed register are shifted out at the SCI_OUT output pin. Preliminary Data Sheet 83 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.5.2 Two-Step Command If the address of a register requires an Index, Read and Write commands must be implemented in two steps. 7.5.2.1 Two-Step Write Command STEP ONE: The value of the Index is written to the Index register at address Index 0/Offset 0. In the example below, the value of the Index is represented by the bits J[7:0]: * Write Index - First Command: Bit 7 Read/ Write 0 * 6 Index 0 5 Offset_ 3 0 4 Offset_ 2 0 3 Offset_ 1 0 2 Offset_ 0 0 1 Fixed 1 0 Don't Care x Data (index): Bit 7 J7 STEP TWO: The data are written to the location of the register, specified by the previously written Index and the Offset represented by the bits A[3:0]: * 6 J6 5 J5 4 J4 3 J3 2 J2 1 J1 0 J0 Write Data - Second Command: Bit 7 Read/ Write 0 * 6 Index 1 5 Offset_ 3 A3 4 Offset_ 2 A2 3 Offset_ 1 A1 2 Offset_ 0 A0 1 Fixed 1 0 Don't Care x Data: Bit 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 In the second command, the index bit (bit 6) is 1, indicating that the Offset A[3:0] is tied to the Index value (which is stored at Index 0/Offset 0) to define the complete address of the register. Preliminary Data Sheet 84 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.5.2.2 Two-Step Read Command A Read command from a location requiring an Index is also processed in two steps: the first command to write the Index value to address Index 0/Offset 0, and a second command which includes the Offset to read the desired register: STEP ONE: Write Index - First Command: Bit 7 Read/ Write 0 * 6 Index 0 5 Offset_ 3 0 4 Offset_ 2 0 3 Offset_ 1 0 2 Offset_ 0 0 1 Fixed 1 0 Don't Care x Contents: Bit 7 J7 STEP TWO: The second step is reading from the location of the register, specified by the previously written Index and the Offset represented by the bits A[3:0]: 6 J6 5 J5 4 J4 3 J3 2 J2 1 J1 0 J0 Read Data - Second Command: * Bit 7 Read/ Write 1 6 Index 1 5 Offset_ 3 A3 4 Offset_ 2 A2 3 Offset_ 1 A1 2 Offset_ 0 A0 1 Fixed 1 0 Don't Care x * Contents: Bit * 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Both commands are transmitted at the SCI_IN input pin; the contents of the addressed register are shifted out at the SCI_OUT output pin. Preliminary Data Sheet 85 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.6 Interrupt Handling The interrupt handling in ALIS V3 is realized by the ALIS firmware. The interrupt sources are sampled once every frame. An interrupt source has to be stable for a minimum of one frame period in order to be detected. In the following example the change of interrupt source 1 is detected. Interrupt source 2 is ignored because its duration is less then a frame hence it is not detected. * AT8 DTprA DTprA! Tphvt of Intr-sources (exact moment depends on Chip-status) Figure 7-1 Scanning of an Interrupt The following table shows the interrupt register (software register) which consists of four static and four dynamic interrupts (for further description of this register see 'R1' on page 6-56). Table 7-4 Interrupt Register R1 Dynamic Interrupts 7 i_cadence 6 i_ring 5 i_cid2 4 i_cid1 3 i_vdd Static Interrupts 2 i_gpio _d 1 i_gpi_ 1_a 0 i_gpi_ 0_a Preliminary Data Sheet 86 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.6.1 Static Interrupts Any change of a static interrupt source longer than two frame periods generates an interrupt. Every detected signal change is indicated by '1' in the corresponding bit in the interrupt register R1. The static interrupts in the interrupt register are reset automatically by reading register R1 from the host. The actual value of the static interrupt sources is available in R13 (see page 6-66). The firmware copies the status of the static interrupt sources to register R13 every frame. * Table 7-5 Interrupt i_gpi_0_a i_gpi_1_a i_gpio_d i_vdd Static Interrupts Bit in Register R1 Bit 0 Bit 1 Bit 2 Bit 3 Description Signal pin 18 "GPI_0_A" at ALIS-A Signal pin 17 "GPI_1_A at ALIS-A Signal pin 8 "GPIO_D" at ALIS-D Indicates that the ALIS-A is power supplied, and the digital isolation interface is running The interrupts i_gpi_0_a, i_gpi_1_a and i_vdd are transferred via the Digital Isolation Interface to the ALIS-D. They are stored in R13 (see page 6-66) (= interrupt source). Preliminary Data Sheet 87 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.6.2 Dynamic Interrupts An event generates an interrupt. Every detected event is indicated by '1' in the corresponding bit in the interrupt register (for further description of this register see 'R1' on page 6-56). The bits in this register are cleared automatically by reading the interrupt register from the host. The interrupt sources of the dynamic interrupts are cleared automatically. Ha Table 7-6 Interrupt i_cid1 Dynamic Interrupts Bit in Register R1 Bit 4 Description First page of the Caller ID buffer is full or end of CID is detected (2 page mode) a) Caller ID buffer is full or end of CID is detected (1 page mode). b) Second page of Caller ID buffer is full or end of CID is detected (2 page mode). Interrupt bases on rings; three modes can be selected (refer to 'R6' on page 6-62): * if auto_ring='1' then - Detection of a valid ring (ring_int='1' in 'R6' on page 6-62) - Detection of the programmed number (n_ring, see 'R5' on page 6-61) of valid rings (ring_int='0' in 'R6' on page 6-62) * if auto_ring='0' then detection of a signal on Tip/Ring (higher than 10 Vrms). Interrupt bases on cadence time out. The timeout can be programmed via 'R8' (see page 6-64). Possible causes: Valid ring not detected within cadence timeout after a valid ring Valid ring not detected within cadence timeout after line reversal/spike. i_cid2 Bit 5 i_ring Bit 6 i_cadence Bit 7 Preliminary Data Sheet 88 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Programming 7.6.3 Interrupt Handling for the Host The host can program the interrupt enable register (see 'R2' on page 6-58) to enable the interrupts with '1' in the corresponding bits. The pin 14 INT of the ALIS-D indicates an interrupt with "low". The host has to read the interrupt register (see 'R1' on page 6-56) to get the information about the source of the interrupt. After reading the interrupt register it is cleared automatically and the pin INT is set to "high". If a static interrupt source causes an interrupt, the host can read the interrupt values register ('R13' on page 6-66) to get the actual value of the corresponding static interrupt source. If all interrupts are disabled, the host still can poll the interrupt register to detect a signal change for a static interrupt source or an event for a dynamic interrupt source. Preliminary Data Sheet 89 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Timing Diagrams 8 8.1 * * Timing Diagrams Input/Output Waveform for AC Tests 2.8 V 0.4 V 2.4 V 0.8 V Test Points 2.4 V 0.8 V Device under Test = 50 pF max C Load Figure 8-1 Waveform for AC Tests During AC-Testing, the inputs are driven at a low level of 0.4 V and a high level of 2.8 V. The timing tests are made at 0.8 V and 2.4 V respectively. 8.2 Reset Timing To Reset the ALIS, pulses applied to the RESET pin must be less than 0.8 V and longer than tRESET,min (t.b.d., about 500 ns). Pulses shorter than tRESET,Ignore (t.b.d., about 100 ns) are ignored. 8.3 * * Serial Control Interface Timing SCI_CS tSU(SCI_CS) tC(SCI_CLK) SCI_CLK tHD(SCI_CS) t SU(SCI_IN) SCI_IN SCI_OUT Figure 8-2 t HD(SCI_IN) t D(SCI_OUT) t D(SCI_OUT_Z) HIGH IMPEDANCE Serial Control Interface Timing Preliminary Data Sheet 90 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Timing Diagrams * Table 8-1 Serial Control Interface Timing Characteristics 99 SCI_CLK need not have constant frequency. These values apply for V and ambient temperature in the range 0 - 70C. Parameter SCI Clock-Cycle Time SCI Clock Duty Cycle SCI frequency Setup Time: SCI_CS until next SCI_CLK Hold Time: last SCI_CLK until SCI_CS Setup Time: SCI_IN valid before SCI_CLK Hold Time: last SCI_CLK until SCI_IN invalid Delay Time: SCI_CLK until SCI_OUT valid Delay Time: last SCI_CLK until SCI_OUT_Z (when SCI_OUT goes to tristate) Symbol min. typ. 50 t.b.d. = 3.3 V 5%, Unit ns % kHz ns ns ns ns Limit Values max. t.b.d. 2048 t.b.d. 488 t.b.d. - tC(SCI_CLK) tSU(SCI_CS) tHD(SCI_CS) tSU(SCI_IN) tHD(SCI_IN) tD(SCI_OUT) t.b.d. 120 60 120 100 40 ns ns tD(SCI_OUT_Z) 13 Note: Switchable SCI_OUT internal pull-up resistor: 660 k Preliminary Data Sheet 91 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Timing Diagrams 8.4 * * Serial Data Interface Timing t W(FSC) FSC t C(FSC) tSU(FSC) tC(SDI_CLK) SDI_CLK t SU(SDI_TX) SDI_TX t HD(SDI_TX) t D(SDI_RX_Z) tD(SDI_RX) High Impedance SDI_RX Figure 8-3 Serial Data Interface Timing Note: SDI_RX goes to tristate on last bit of 16 transferred bits in a FSC frame. Preliminary Data Sheet 92 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Timing Diagrams * Table 8-2 Serial Data Interface Timing Characteristics 99 These values apply for V Parameter SDI Clock-Cycle Time SDI Clock Duty Cycle SDI Clock frequency = 3.3 V 5%, and ambient temperature in the range 0 - 70C. Symbol Limit Values min. typ. 50 125 8 max. 55 2048 139 32 ns % kHz s kHz 488 45 256 31 7.2 Unit tC(SDI_CLK) Frame Synchronization Clock (FSC)- tC(FSC) Cycle Time FSC frequency FSC Pulse Width (required as input, in Slave Mode) tW(FSC) tC(SDI_CLK) tC(SDI_CLK) t.b.d. t.b.d. t.b.d. 0 t.b.d. 0.5* t.b.d. ns ns ns ns ns 40 ns FSC Pulse Width tW(FSC) (produced as output, in Master Mode) Setup Time: SDI_TX valid before SDI_CLK Hold Time: last SDI_CLK until SDI_TX invalid Delay Time: SDI_CLK until SDI_RX valid Delay Time: last SDI_CLK until FSC Setup Time: FSC until next SDI_CLK Delay Time: last SDI_CLK until SDI_RX_Z (when SDI_RX goes to tristate) tSU(SDI_TX) tHD(SDI_TX) tD(SDI_RX) tD(FSC) tSU(FSC) tC(SDI_CLK) tD(SDI_RX_Z) 13 The frame synchronization clock-cycle time is 1/fFSC, where fFSC is the sampling rate. In turn, fFSC is controlled by the parameter fac_fsc. See Chapter 3.3.13. Note: Switchable SDI_RX internal pull-up resistor: 660 k Preliminary Data Sheet 93 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Electrical Characteristics 9 9.1 Table 9-1 Parameter Electrical Characteristics Recommended Operating Conditions Recommended Operating Conditions Symbol min. Conditions typ. 3.3 4.25 0 24 45 24.576 50 70 33 55 20 max. 3.46 V V C MHz % ns 3.14 Unit Digital Supply Voltage ALIS-D Analog Supply Voltage ALIS-A Ambient Temperature under bias Operating Frequency Clock Duty Cycle Signal Rise and Fall Time VDD VDDA TA fMCLK t,t s Note: Extended operation outside the recommended limits may degrade performance and affect reliability. Preliminary Data Sheet 94 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Electrical Characteristics 9.2 Table 9-2 Parameter Extreme Absolute Range Extreme Absolute Range Symbol min. Range max. 4.5 7.0 V V V V mA C C W -0.3 -0.3 -0.3 -0.3 -5 -60 0 Unit Ratings in the following table, Table 9-2, apply to both ALIS-A and ALIS-D. Digital Supply Voltage Analog Supply Voltage Analog Input Voltage Digital Input Voltages DC Output Current Storage Temperature Ambient Temperature under bias Maximum Power Dissipation VDD VDDA Vin VDin Iout TST TA PDmax V 996 + 0.3 5.5 5 125 70 1 Note: Stresses above those listed may cause permanent damage to the device. Extended operation at the absolute maximum levels may affect device reliability. Preliminary Data Sheet 95 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Electrical Characteristics 9.3 9.3.1 Table 9-3 DC Characteristics ALIS-A DC Characteristics DC Characteristics of the ALIS-A 996 These values apply for V Parameter VDDA Supply Current = 4.25 V, and ambient temperature in the range 0 - 70C. Symbol Conditions Spec. Limits min. typ. max. 3 mA Unit - in Ringing state (AC current during ringing burst, due to synthesized ringer impedance) - in Conversation state (DC current, due to synthesized DC characteristics) IDDA1 Vring = 60 Vdc + 90 Vrms f = 25 - 50 Hz vt 2.5 IDDA2 7 10 mA - in Pulse Dialing break state IDDA3 General Purpose Inputs and Outputs Low-level Input Voltage: VIL - at pins: Test, GPI_0_A, and GPI_1_A High-level Input Voltage: VIH - at pins: Test, GPI_0_A, and GPI_1_A Low-level Output Voltage: - at pins: GPO_0_A, and GPO_1Q_A High-level Output Voltage: - at pins: GPO_0_A, and GPO_1Q_A Input Current Low Input Current High VTIP/RING = 60 Vdc 500 0.8 A V 2.0 V VOL I PG = 5 mA 0.5 V VOH I PC = -5 mA 3.25 V IIL IIH V = GNDA DG 1 1 A A V =V DCA 996 Preliminary Data Sheet 96 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Electrical Characteristics Table 9-3 DC Characteristics of the ALIS-A (cont'd) 996 These values apply for V Parameter = 4.25 V, and ambient temperature in the range 0 - 70C. Symbol Conditions Spec. Limits min. typ. max. M Unit Input DC Resistance (on Tip/Ring) - in Idle state RIN Hook switch must be open, so infinite input resistance See Chapter 5.1.3.1 During the "make" period 5 - in Conversation state - in Pulse Dialing state Power-Up time RIN RIN tPU W 200 100 W ms Preliminary Data Sheet 97 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Electrical Characteristics 9.3.2 Table 9-4 ALIS-D DC Characteristics DC Characteristics of the ALIS-D 99 These characteristics apply when V = 3.3 V 5%, and for ambient temperature in the range 0 - 70 C. All digital inputs are 5V tolerant. Parameter Supply Current: - in Sleep state - in Idle state - in Ringing state - in Caller-ID state - in Conversation state - in Pulse Dialing state Low-level Input Voltage: - at CMOS Inputs: SCI_CLK, SCI_CS, SCI_IN, SDI_CLK, SDI_TX, MODE, FSC - at CMOS Input: RESET - at clock Input: MCLK1 High-level Input Voltage: - at CMOS Inputs: SCI_CLK, SCI_CS, SCI_IN, SDI_CLK, SDI_TX, MODE, FSC - at CMOS Input: RESET - at clock Input: MCLK1 Low-level Output Voltage: - at pins: SCI_OUT, INT, SDI_RX, FSC Symbol Conditions = 3.3 V, no load 99 Spec. Limits min. typ. max. Unit V IDD0 IDD1 IDD2 IDD3 IDD4 IDD5 fMCLK = 24 MHz < 10 50 3.5 8 8 13 8 10 15 15 25 15 A mA mA mA mA mA fMCLK = 24 MHz fMCLK = 24 MHz fMCLK = 24 MHz fMCLK = 24 MHz VIL1 0.8 V VIL3 VIL2 VIH1 2.0 0.8 0.5 5.5 V V V VIH2 VIH3 VOL I = 5 mA 2.0 2.0 5.5 5.5 0.5 V V V PG Preliminary Data Sheet 98 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Electrical Characteristics Table 9-4 DC Characteristics of the ALIS-D (cont'd) 99 These characteristics apply when V = 3.3 V 5%, and for ambient temperature in the range 0 - 70 C. All digital inputs are 5V tolerant. Parameter High-level Output Voltage: - at pins: SCI_OUT, SDI_RX, FSC Input Current Low: - at CMOS inputs: SCI_CLK, GPIO_D, SCI_CS, SCI_IN, SDI_CLK, SDI_TX, MODE, FSC, RESET Input Current High: - at CMOS Inputs: SCI_CLK, GPIO_D, SCI_CS, SCI_IN, SDI_CLK, SDI_TX, MODE, FSC, RESET. Tristate Current Low: Tristates, Bidirectionals: SCI_OUT, FSC, INT1) Tristate Current High: Tristates, Bidirectionals: SCI_OUT, FSC 1) Symbol Conditions Spec. Limits min. typ. max. Unit VOH I PCA = -5 mA VDD -0.5 V IIL V = GND DG 1 A IIH V =V DCA 99 1 A IOZL V = GND DG 1 A IOZH V =V DC 99 1 A 33 k internal pull-up resistor not taken into consideration. Note: For load currents see "DC Output Current" in Table 9-2. Preliminary Data Sheet 99 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Electrical Characteristics 9.4 * * * * * * * * AC Characteristics These characteristics apply under the following test conditions: Ambient temperature in the range 0 - 70 C. V = 3.3 V 5%. Line impedance Z = 600 0.1%. The frequency of the test signal is 1004 Hz. V is programmed to 4.25 V. The analog voltage level is defined as 0 dBm = 0.775 Vrms when loaded at 600 . The digital voltage level is defined such that 0 dBm0 = -3 dB below Full Scale. The ALIS-D gain parameters are set such that AGX = 0 dB = AGR, and an analog signal of 0 dBm corresponds to a digital signal of 0 dBm0. 99 G 996 Table 9-5 AC Characteristics Ripple: 0 - 150 kHz; 70 mVrms 300 Hz - 3.4 kHz 3.4 - 150 kHz 996 Power Supply Rejection Ratio Either Supply/Direction Either Supply/Direction Ring Threshold PSRR PSRR 40 25 10 dB dB Vrms VRThresh V = 4.25 V 9.4.1 * Absolute Gain Error Absolute Gain Error Symbol Test Condition AE_R AE_R AE_X AE_X -10 dBm analog input -10 dBm analog input -10 dBm0 digital input -10 dBm0 digital input Ambient Temperature 25 C 0 - 70 C 25 C 0 - 70 C Limit Values min. -1 -1.2 -1 -1.2 typ. 0.5 0.7 0.5 0.7 max +1 +1.2 +1 +1.2 dB dB dB dB Unit Table 9-6 Direction Receive Receive Transmit Transmit Preliminary Data Sheet 100 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Electrical Characteristics 9.4.2 * Gain Tracking Gain Tracking Symbol Test Condition GT_R GT_R GT_R GT_X GT_X GT_X 0 to -10 dBm analog input -10 to -40 dBm analog input -40 to -50 dBm analog input 0 to -10 dBm0 digital input -10 to -40 dBm0 digital input -40 to -50 dBm0 digital input Limit Values min. typ. max. dB dB dB dB dB dB -0.15 -0.15 -0.3 -0.5 -0.1 -0.5 0.01 0.15 0.01 0.15 0.07 0.3 0.05 0.5 0.07 0.1 0.3 0.5 Unit Table 9-7 Direction Receive Receive Receive Transmit Transmit Transmit Preliminary Data Sheet 101 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Package Outlines 10 * Package Outlines P-TSSOP24 PSB 4595 (Plastic Thin Shrink Small Outline Package) * * P-TSSOP28 PSB 4596 (Plastic Thin Shrink Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Preliminary Data Sheet 102 Dimensions in mm 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Appendix 11 Appendix Glossary * AC ADC ALIS CRAM DAA DAC DC DFS DSP DTMF FCC ISDN ITU ITU-T SCI SDI USB Alternating Current Analog-to-Digital Conversion Analog Line Interface Solution, PSB 4595 and PSB 4596 Coefficient RAM (Random Access Memory) Data Access Arrangement Digital-to-Analog Conversion Direct Current Digital Filter Structure Digital Signal Processing Dual Tone Multi-Frequency Federal Communications Commission Integrated Services Digital Network International Telecommunication Union International Telecommunication Union - TSB (Telecommunications Standardization Bureau) Serial Control Interface Serial Data Interface Universal Serial Bus Preliminary Data Sheet 103 04.99 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Index 12 A Index DSP Additional Codec 40 ALIS-D Configuration 80 Determination of the State 81 Reset 79 Analog supply voltage 16, 94, 95, 100 Analog/Digital Conversion 23 Auto Sleep 28, 61, 62 Automatic Call Processing 28, 56, 61, 62 Automatic Power mode switching 81 13, 23 flag 81 DTMF 10, 21, 47, 72 Dual-Line Modem 41 Duration of the boot sequence Dynamic interrupts 86, 88 78 E External Clock 18, 26, 33, 43, 75 External Crystal 18, 25, 29, 43, 68, 75 External metering filter 47 F Fractional Divider 80 Frame Synchronization 18, 27, 34, 93 FSC 18, 34, 37, 41, 61, 76, 93, 98 FSK 23, 47 B Bandpass filtering 21, 23 C 53, 67 buffer 56, 58 comparator 20 data 21, 63 RAM 21, 63 receiver 11 signal 23, 28, 33, 48, 63, 73 state 28, 60 storage 9, 11, 23, 28 timing 47 Capacitive interface 49 Central Office 47 Channel equalization 23 Commands 82-84 Configuration of ALIS-D 80, 81 CRAM 23, 28, 51, 72 write 81 Caller-ID G Gain parameters 100 H High-pass filter 31 Host 28, 33, 35, 40, 42, 43, 50, 63 interface 27, 37 Hybrid Circuit 23 I Impedance matching 23 Inductive interface 49 Interface Configuration 78 Internal Clock 25, 29, 74 Interrupt handling 86, 89 Interrupt register 86 Interrupt source 86 D Data Access Arrangement 10, 21 Data pump 21, 28, 34, 43 Digital isolation interface 10, 13, 17, 20, 21, 24 Digital supply voltage 18, 94, 95 M Master Clock 18, 25, 29, 68 Master mode 79 MCLK 19, 25, 27, 51 Mode Master 19, 27, 34, 35, 39, 40, 04.99 Preliminary Data Sheet 104 PSB 4595 / PSB 4596 Analog Line Interface Solution - ALIS Index 42, 51, 93 Multiplex 18, 19, 27, 33, 34, 37, 38, 39, 40, 51 Non-Multiplex 19, 27, 33, 34, 42, 43, 51 Slave 19, 27, 34, 35, 36, 39, 40, 43, 51, 93 Multiplex mode 79 Serial Data Interface 14, 18, 21, 62, 71, 79 Master mode 35 Multiplex mode 37 Non-multiplex mode 43 Slave mode 36 Setup of ALIS-D 79 State Caller-ID 28, 98 Conversation 29, 46, 60, 62, 96, 97, 98 Idle 28, 51, 60, 62, 65, 97, 98 Pulse dialing 29, 60, 65, 96, 97, 98 Ringing 28, 60, 65, 96, 98 Sleep 19, 21, 28, 29, 60, 61, 62, 98 Static interrupts 86 N Non-Automatic Call Processing 28 O Out-of-Band receive 31 Out-of-Band transmit 32 Oversampling 23 factor 71 factor "K" 78, 80 parameter 25 P PC-Card 11 PCI 14 Phase-Locked Loop Power management 10, 27 11 T Transistor 16, 45, 47 U USB 14 R Read command 37, 42, 82, 85 Reset 18, 28, 29, 37, 51, 90 Ring detection 21, 23 detector 9, 10 Interrupt 81 W Write command 37, 82, 85 S Sampling frequency 27, 71 rate 10, 26, 41, 93 Serial Control Interface 21, 50 Idle state 28 Multiplex mode 37 Non-multiplex mode 19, 42 Serial Data 74 Preliminary Data Sheet 105 04.99 |
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